Offset
Name
Bit Pos.
0x98
7:0
BKUP[7:0]
0x99
15:8
BKUP[15:8]
0x9A
23:16
BKUP[23:16]
0x9B
31:24
BKUP[31:24]
0x9C
7:0
BKUP[7:0]
0x9D
15:8
BKUP[15:8]
0x9E
23:16
BKUP[23:16]
0x9F
31:24
BKUP[31:24]
25.12. Register Description - CLOCK
This Register Description section is valid if the RTC is in Clock/Calendar mode (CTRLA.MODE=2).
Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition,
the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be
accessed directly.
Some registers require synchronization when read and/or written. Synchronization is denoted by the
"Read-Synchronized" and/or "Write-Synchronized" property in each individual register description.
Optional write-protection by the Peripheral Access Controller (PAC) is denoted by the "PAC Write-
Protection" property in each individual register description.
Some registers are enable-protected, meaning they can only be written when the module is disabled.
Enable-protection is denoted by the "Enable-Protected" property in each individual register description.
Atmel SAM L22G / L22J / L22N [DATASHEET]
Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016
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