32.8.2. Control B
Name:
CTRLB
Offset:
0x04
Reset:
0x00000000
Property:
PAC Write-Protection, Enable-Protected, Write-Synchronized
Bit
31
30
29
28
27
26
25
24
Access
Reset
Bit
23
22
21
20
19
18
17
16
RXEN
TXEN
Access
R/W
R/W
Reset
0
0
Bit
15
14
13
12
11
10
9
8
PMODE
ENC
SFDE
COLDEN
Access
R/W
R/W
R/W
R/W
Reset
0
0
0
0
Bit
7
6
5
4
3
2
1
0
SBMODE
CHSIZE[2:0]
Access
R/W
R/W
R/W
R/W
Reset
0
0
0
0
Bit 17 – RXEN: Receiver Enable
Writing '0' to this bit will disable the USART receiver. Disabling the receiver will flush the receive buffer
and clear the FERR, PERR and BUFOVF bits in the STATUS register.
Writing '1' to CTRLB.RXEN when the USART is disabled will set CTRLB.RXEN immediately. When the
USART is enabled, CTRLB.RXEN will be cleared, and SYNCBUSY.CTRLB will be set and remain set
until the receiver is enabled. When the receiver is enabled, CTRLB.RXEN will read back as '1'.
Writing '1' to CTRLB.RXEN when the USART is enabled will set SYNCBUSY.CTRLB, which will remain
set until the receiver is enabled, and CTRLB.RXEN will read back as '1'.
This bit is not enable-protected.
Value
Description
0
The receiver is disabled or being enabled.
1
The receiver is enabled or will be enabled when the USART is enabled.
Bit 16 – TXEN: Transmitter Enable
Writing '0' to this bit will disable the USART transmitter. Disabling the transmitter will not become effective
until ongoing and pending transmissions are completed.
Writing '1' to CTRLB.TXEN when the USART is disabled will set CTRLB.TXEN immediately. When the
USART is enabled, CTRLB.TXEN will be cleared, and SYNCBUSY.CTRLB will be set and remain set until
the transmitter is enabled. When the transmitter is enabled, CTRLB.TXEN will read back as '1'.
Atmel SAM L22G / L22J / L22N [DATASHEET]
Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016
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