Atmel ATSAML22G16A-AUT, Manual

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arriving interrupts. Refer to NVIC-Nested Vector Interrupt Controller and the Cortex-M0+
Technical Reference Manual for details ( http://www.arm.com ).
Note: When the CPU frequency is much higher than the APB frequency it is recommended
to insert a memory read barrier after each CPU write to registers mapped on the APB. Failing
to do so in such conditions may lead to unexpected behavior such as e.g. re-entering a
peripheral interrupt handler just after leaving it.
• System Timer (SysTick)
– The System Timer is a 24-bit timer clocked by CLK_CPU that extends the functionality of both
the processor and the NVIC. Refer to the Cortex-M0+ Technical Reference Manual for details
(
http://www.arm.com ).
• System Control Block (SCB)
– The System Control Block provides system implementation information, and system control.
This includes configuration, control, and reporting of the system exceptions. Refer to the
Cortex-M0+ Devices Generic User Guide for details (
http://www.arm.com ).
• Micro Trace Buffer (MTB)
– The CoreSight MTB-M0+ (MTB) provides a simple execution trace capability to the Cortex-
M0+ processor. Refer to section
MTB-Micro Trace Buffer and the CoreSight MTB-M0+
Technical Reference Manual for details ( http://www.arm.com ).
• Memory Protection Unit (MPU)
– The Memory Protection Unit divides the memory map into a number of regions, and defines
the location, size, access permissions and memory attributes of each region. Refer to the
Cortex-M0+ Devices Generic User Guide for details (
http://www.arm.com )
11.1.3. Cortex M0+ Address Map
Table 11-2. Cortex-M0+ Address Map
Address Peripheral
0xE000E000 System Control Space (SCS)
0xE000E010 System Timer (SysTick)
0xE000E100 Nested Vectored Interrupt Controller (NVIC)
0xE000ED00 System Control Block (SCB)
0x41006000 Micro Trace Buffer (MTB)
Related Links
Product Mapping on page 38
11.1.4. I/O Interface
The device allows direct access to PORT registers. Accesses to the AMBA
®
AHB-Lite
™
and the single
cycle I/O interface can be made concurrently, so the Cortex M0+ processor can fetch the next instructions
while accessing the I/Os. This enables single cycle I/O access to be sustained for as long as necessary.
Related Links
CPU Local Bus on page 541
PORT: IO Pin Controller on page 538
Atmel SAM L22G / L22J / L22N [DATASHEET]
Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016
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