Atmel ATSAML22G16A-AUT, Manual

Page: 499 / 1231

27.6.2. Basic Operation
27.6.2.1. Initialization
The EIC must be initialized in the following order:
1. Enable CLK_EIC_APB
2. If required, configure the NMI by writing the Non-Maskable Interrupt Control register ( NMICTRL )
3. When the NMI is used or synchronous edge detection or filtering are required, enable GCLK_EIC
or CLK_ULP32K.
GCLK_EIC is used when a frequency higher than 32KHz is required for filtering, CLK_ULP32K is
recommended when power consumption is the priority. For CLK_ULP32K write a '1' to the Clock
Selection bit in the Control A register (
CTRLA .CKSEL). Optionally, enable the asynchronous mode.
4. Configure the EIC input sense and filtering by writing the Configuration n register ( CONFIG0,
CONFIG1 ).
5. Enable the EIC.
The following bits are enable-protected, meaning that it can only be written when the EIC is disabled
(
CTRLA .ENABLE=0):
• Clock Selection bit in Control A register ( CTRLA .CKSEL)
The following registers are enable-protected:
• Event Control register ( EVCTRL )
• Configuration n register ( CONFIG0 , CONFIG1 ...)
• External Interrupt Asynchronous Mode register ( ASYNCH )
Enable-protected bits in the CTRLA register can be written at the same time when setting
CTRLA .ENABLE to '1', but not at the same time as CTRLA .ENABLE is being cleared.
Enable-protection is denoted by the "Enable-Protected" property in the register description.
27.6.2.2. Enabling, Disabling, and Resetting
The EIC is enabled by writing a '1' the Enable bit in the Control A register ( CTRLA .ENABLE). The EIC is
disabled by writing CTRLA .ENABLE to '0'.
The EIC is reset by setting the Software Reset bit in the Control register ( CTRLA .SWRST). All registers in
the EIC will be reset to their initial state, and the EIC will be disabled.
Refer to the CTRLA register description for details.
27.6.3. External Pin Processing
Each external pin can be configured to generate an interrupt/event on edge detection (rising, falling or
both edges) or level detection (high or low). The sense of external interrupt pins is configured by writing
the Input Sense x bits in the Config n register (
CONFIGn .SENSEx). The corresponding interrupt flag
( INTFLAG .EXTINT[x]) in the Interrupt Flag Status and Clear register (INTFLAG) is set when the interrupt
condition is met.
When the interrupt flag has been cleared in edge-sensitive mode, INTFLAG .EXTINT[x] will only be set if a
new interrupt condition is met. In level-sensitive mode, when interrupt has been cleared,
INTFLAG .EXTINT[x] will be set immediately if the EXTINTx pin still matches the interrupt condition.
Each external pin can be filtered by a majority vote filtering, clocked by GCLK_EIC or CLK_ULP32K.
Filtering is enabled if bit Filter Enable x in the Configuration n register (
CONFIGn .FILTENx) is written to
'1'. The majority vote filter samples the external pin three times with GCLK_EIC or CLK_ULP32K and
outputs the value when two or more samples are equal.
Atmel SAM L22G / L22J / L22N [DATASHEET]
Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016
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