Related Links
37.5.3. Clocks
The TRNG bus clock (CLK_TRNG_APB) can be enabled and disabled in the Main Clock module, and the
default state of CLK_TRNG_APB can be found in
Peripheral Clock Masking
.
Related Links
on page 145
37.5.4. DMA
Not applicable.
37.5.5. Interrupts
The interrupt request line is connected to the interrupt controller. Using the TRNG interrupt(s) requires the
interrupt controller to be configured first. Refer to NVIC - Nested Interrupt
Nested Vector Interrupt
Controller
for details.
Related Links
Nested Vector Interrupt Controller
on page 44
37.5.6. Events
The events are connected to the Event System. Refer to
EVSYS – Event System
for details on how to
configure the Event System.
Related Links
37.5.7. Debug Operation
When the CPU is halted in debug mode the TRNG continues normal operation. If the TRNG is configured
in a way that requires it to be periodically serviced by the CPU through interrupts or similar, improper
operation or data loss may result during debugging.
37.5.8. Register Access Protection
All registers with write-access are optionally write-protected by the Peripheral Access Controller (PAC),
except the following register:
Interrupt Flag Status and Clear (INTFLAG) register
Optional write-protection by the Peripheral Access Controller (PAC) is denoted by the "PAC Write-
Protection" property in each individual register description.
37.5.9. Analog Connections
Not applicable.
37.6. Functional Description
37.6.1. Principle of Operation
As soon as the TRNG is enabled, the module automatically provides a new 32-bit random number every
84 CLK_TRNG_APB clock cycles. When new data is available, an optional interrupt or event can be
generated.
Atmel SAM L22G / L22J / L22N [DATASHEET]
Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016
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