Atmel ATSAML22G16A-AUT, Manual

Page: 833 / 1231

Offset Name Bit Pos.
0x54
...
0x63
Reserved
0x64
PATTBUF
7:0 PGEB7 PGEB6 PGEB5 PGEB4 PGEB3 PGEB2 PGEB1 PGEB0
0x65 15:8 PGVB7 PGVB6 PGVB5 PGVB4 PGVB3 PGVB2 PGVB1 PGVB0
0x66
...
0x6B
Reserved
0x6C
PERBUF
7:0 PERBUF[1:0] DITHERBUF[5:0]
0x6D 15:8 PERBUF[9:2]
0x6E 23:16 PERBUF[17:10]
0x6F 31:24 PERBUF[25:18]
0x70
CCBUF0
7:0 CCBUF[1:0] DITHERBUF[5:0]
0x71 15:8 CCBUF[9:2]
0x72 23:16 CCBUF[17:10]
0x73 31:24 CCBUF[25:18]
0x74
CCBUF1
7:0 CCBUF[1:0] DITHERBUF[5:0]
0x75 15:8 CCBUF[9:2]
0x76 23:16 CCBUF[17:10]
0x77 31:24 CCBUF[25:18]
0x78
CCBUF2
7:0 CCBUF[1:0] DITHERBUF[5:0]
0x79 15:8 CCBUF[9:2]
0x7A 23:16 CCBUF[17:10]
0x7B 31:24 CCBUF[25:18]
0x7C
CCBUF3
7:0 CCBUF[1:0] DITHERBUF[5:0]
0x7D 15:8 CCBUF[9:2]
0x7E 23:16 CCBUF[17:10]
0x7F 31:24 CCBUF[25:18]
36.8. Register Description
Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition,
the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be
accessed directly.
Some registers require synchronization when read and/or written. Synchronization is denoted by the
"Read-Synchronized" and/or "Write-Synchronized" property in each individual register description.
Optional write-protection by the Peripheral Access Controller (PAC) is denoted by the "PAC Write-
Protection" property in each individual register description.
Some registers are enable-protected, meaning they can only be written when the module is disabled.
Enable-protection is denoted by the "Enable-Protected" property in each individual register description.
Atmel SAM L22G / L22J / L22N [DATASHEET]
Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016
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