When the USART is the receiver and it detects a parity error, the parity error bit in the Status Register
(STATUS.PERR) is set and the character is not written to the receive FIFO.
Receive Error Counter
The receiver also records the total number of errors (receiver parity errors and NACKs from the remote
transmitter) up to a maximum of 255. This can be read in the Receive Error Count (RXERRCNT) register.
RXERRCNT is automatically cleared on read.
Receive NACK Inhibit
The receiver can also be configured to inhibit error generation. This can be achieved by setting the Inhibit
Not Acknowledge (CTRLC.INACK) bit. If CTRLC.INACK is 1, no error signal is driven on the I/O line even
if a parity error is detected. Moreover, if CTRLC.INACK is set, the erroneous received character is stored
in the receive FIFO, and the STATUS.PERR bit is set. Inhibit not acknowledge (CTRLC.INACK) takes
priority over disable successive receive NACK (CTRLC.DSNACK).
Transmit Character Repetition
When the USART is transmitting a character and gets a NACK, it can automatically repeat the character
before moving on to the next character. Repetition is enabled by writing the Maximum Iterations register
(CTRLC.MAXITER) to a non-zero value. The USART repeats the character the number of times specified
in CTRLC.MAXITER.
When the USART repetition number reaches the programmed value in CTRLC.MAXITER, the
STATUS.ITER bit is set and the internal iteration counter is reset. If the repetition of the character is
acknowledged by the receiver before the maximum iteration is reached, the repetitions are stopped and
the iteration counter is cleared.
Disable Successive Receive NACK
The receiver can limit the number of successive NACKs sent back to the remote transmitter. This is
programmed by setting the Disable Successive NACK bit (CTRLC.DSNACK). The maximum number of
NACKs transmitted is programmed in the CTRLC.MAXITER field. As soon as the maximum is reached,
the character is considered as correct, an acknowledge is sent on the line, the STATUS.ITER bit is set
and the internal iteration counter is reset.
32.6.3.7. Collision Detection
When the receiver and transmitter are connected either through pin configuration or externally, transmit
collision can be detected after selecting the Collision Detection Enable bit in the CTRLB register
(CTRLB.COLDEN=1). To detect collision, the receiver and transmitter must be enabled (CTRLB.RXEN=1
and CTRLB.TXEN=1).
Collision detection is performed for each bit transmitted by comparing the received value with the transmit
value, as shown in the figure below. While the transmitter is idle (no transmission in progress), characters
can be received on RxD without triggering a collision.
Figure 32-18. Collision Checking
8-bit character, single stop bit
Collision checked
TXD
RXD
Atmel SAM L22G / L22J / L22N [DATASHEET]
Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016
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