The clock division factor DIV is selected by the Clock Divider bits CTRLA.CKDIV[2:0]. The division factor
is DIV=CKDIV[2:0]+1. The duty ratio NB_COM is selected by writing to the Duty Ratio bits in the Control
A register (CTRLA.DUTY).
The resulting frame rate is calculated according to this formula:
FrameRate =
� CLK_SLCD_OSC
PVAL × DIV × NB_COM
Table 43-4. Examples of Frame Rates for f(CLK_SLCD_OSC) = 32768Hz
Prescaler Value
(PVAL)
CKDIV[2:0]
DIV
NB_COM
Frame Rate
128
0x7
8
1
32 Hz
128
0x2
3
1
85.3 Hz
64
0x7
8
2
32 Hz
64
0x2
3
2
85.3 Hz
64
0x4
5
3
34.1 Hz
32
0x3
4
3
85.3 Hz
32
0x7
8
4
32 Hz
32
0x2
3
4
85.3 Hz
32
0x4
5
6
34.1 Hz
16
0x3
4
6
85.3 Hz
16
0x7
8
8
32 Hz
16
0x2
3
8
85.3 Hz
43.6.1.6. LCD Pins Selection
Selection of maximum 48 segment/common lines from 52 LCD pins
There are 52 LCD pins (LPx), of which up to 48 LCD pins can be enabled or disabled individually
according to the LCD glass. Each LCD pin can be configured as frontplane (SEG) or backplane (COM),
offering various configurations. The maximum number of SEG lines and COM lines are defined in the
table below.
Table 43-5. Maximum Number of COM and SEG Lines
Duty
#COM Lines
Max #SEG Lines
Static
1
44
1/2
2
44
1/3
3
44
1/4
4
44
1/6
6
42
1/8
8
40
In order to enable an LCD pin, Write a '1' to the corresponding bit in the corresponding register:
Atmel SAM L22G / L22J / L22N [DATASHEET]
Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016
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