USB Clock Recovery Module
USB Clock Recovery mode can be used to create the 48MHz USB clock from the USB Start Of Frame
(SOF). This mode is enabled by writing a '1' to both the USB Clock Recovery Mode bit and the Mode bit
in DFLL Control register (DFLLCTRL.USBCRM and DFLLCTRL.MODE).
The SOF signal from USB device will be used as reference clock (CLK_DFLL_REF), ignoring the
selected generic clock reference. When the USB device is connected, a SOF will be sent every 1ms, thus
DFLLVAL.MUX bits should be written to 0xBB80 to obtain a 48MHz clock.
In USB clock recovery mode, the DFLLCTRL.BPLCKC bit state is ignored, and the value stored in the
DFLLVAL.COARSE will be used as final Coarse Value. The COARSE calibration value can be loaded
from NVM OTP row by software. The locking procedure will also go instantaneously to the fine lock
search.
The DFLLCTRL.QLDIS bit must be cleared and DFLLCTRL.CCDIS should be set to speed up the lock
phase. The DFLLCTRL.STABLE bit state is ignored, an auto jitter reduction mechanism is used instead.
Wake from Sleep Modes
DFLL48M can optionally reset its lock bits when it is disabled. This is configured by the Lose Lock After
Wake bit in the DFLL Control register (DFLLCTRL.LLAW).
If DFLLCTRL.LLAW is zero, the DFLL48M will be re-enabled and start running with the same
configuration as before being disabled, even if the reference clock is not available. The locks will not be
lost. After the reference clock has restarted, the fine lock tracking will quickly compensate for any
frequency drift during sleep if DFLLCTRL.STABLE is zero.
If DFLLCTRL.LLAW is '1' when disabling the DFLL48M, the DFLL48M will lose all its locks, and needs to
regain these through the full lock sequence.
Accuracy
There are three main factors that determine the accuracy of
F
clkdfll48m
. These can be tuned to obtain
maximum accuracy when fine lock is achieved.
•
Fine resolution. The frequency step between two Fine values. This is relatively smaller for higher
output frequencies.
•
Resolution of the measurement: If the resolution of the measured
F
clkdfll48m
is low, i.e., the ratio
between the CLK_DFLL48M frequency and the CLK_DFLL48M_REF frequency is small, the
DFLL48M might lock at a frequency that is lower than the targeted frequency. It is recommended to
use a reference clock frequency of 32KHz or lower to avoid this issue for low target frequencies.
•
The accuracy of the reference clock.
21.6.6. Digital Phase Locked Loop (DPLL) Operation
The task of the DPLL is to maintain coherence between the input (reference) signal and the respective
output frequency, CLK_DPLL, via phase comparison. The DPLL controller supports three independent
sources of reference clocks:
•
XOSC32K: this clock is provided by the 32K External Crystal Oscillator (XOSC32K).
•
XOSC: this clock is provided by the External Multipurpose Crystal Oscillator (XOSC).
•
GCLK: this clock is provided by the Generic Clock Controller.
When the controller is enabled, the relationship between the reference clock frequency and the output
clock frequency is:
�
CK
= �
CKR
× LDR + 1 + LDRFRAC
16
×
1
2
PRESC
Atmel SAM L22G / L22J / L22N [DATASHEET]
Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016
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