�
CLK_MSR
= VALUE
REFNUM �
CLK_REF
Note:
In order to make sure the measurement result (
.VALUE) is valid, the overflow status
(
.OVF) should be checked.
In case an overflow condition occurred, indicated by the Overflow bit in the STATUS register
(
.OVF), either the number of reference clock cycles must be reduced (
faster reference clock must be configured. Once the configuration is adjusted, clear the overflow status by
writing a '1' to
.OVF. Then another measurement can be started by writing a '1' to
.START.
18.6.3. DMA Operation
Not applicable.
18.6.4. Interrupts
The FREQM has one interrupt source:
•
DONE: A frequency measurement is done
Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status
and Clear (
) register is set when the interrupt condition occurs. Each interrupt can be individually
enabled by writing a '1' to the corresponding bit in the Interrupt Enable Set (
) register, and
disabled by writing a '1' to the corresponding bit in the Interrupt Enable Clear (
An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled.
The interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled, or the
FREQM is reset. See
for details on how to clear interrupt flags. All interrupt requests from the
peripheral are ORed together on system level to generate one combined interrupt request to the NVIC.
The user must read the
register to determine which interrupt condition is present.
Note that interrupts must be globally enabled for interrupt requests to be generated.
18.6.5. Events
Not applicable.
18.6.6. Sleep Mode Operation
The FREQM will continue to operate in idle sleep modes where the selected source clock is running. The
FREQM’s interrupts can be used to wake up the device from idle sleep modes.
For lowest chip power consumption in sleep modes, FREQM should be disabled before entering a sleep
mode.
Related Links
18.6.7. Synchronization
Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers
need to be synchronized when written or read.
The following bits and registers are write-synchronized:
•
Software Reset bit in Control A register (CTRLA.SWRST)
•
Enable bit in Control A register (CTRLA.ENABLE)
Required write-synchronization is denoted by the "Write-Synchronized" property in the register
description.
Atmel SAM L22G / L22J / L22N [DATASHEET]
Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016
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