Enable-protection is denoted by the Enable-Protected property in the register description.
38.6.2.2. Enabling, Disabling, and Resetting
The AES module is enabled by writing a one to the Enable bit in the Control A register (CTRLA.ENABLE).
The module is disabled by writing a zero to CTRLA.ENABLE. The module is reset by writing a one to the
Software Reset bit in the Control A register (CTRLA.SWRST).
38.6.2.3. Basic Programming
The CIPHER bit in the Control A Register (CTRLA.CIPHER) allows selection between the encryption and
the decryption processes. The AES is capable of using cryptographic keys of 128/192/256 bits to encrypt
and decrypt data in blocks of 128 bits. The Key Size (128/192/256) can be programmed in the KEYSIZE
field in the Control A Register (CTRLA.KEYSIZE). This 128-bit/192-bit/256-bit key is defined in the Key
Word Registers (KEYWORDx). By setting the XORKEY bit of CTRLA register, keyword can be updated
with the resulting XOR value of user keyword and previous keyword content.
The input data for processing is written to a data buffer consisting of four 32-bit registers through the Data
register address. The data buffer register (note that input and output data shares the same data buffer
register) that is written to when the next write is performed is indicated by the Data Pointer in the Data
Buffer Pointer (DATABUFPTR) register. This field is incremented by one or wrapped by hardware when a
write to the DATA register address is performed. This field can also be programmed, allowing the user
direct control over which input buffer register to write to. Note that when AES module is in the CFB
operation mode with the data segment size less than 128 bits, the input data must be written to the first
(DATABUFPTR = 0) and/or second (DATABUFPTR = 1) input buffer registers (see
The input to the encryption processes of the CBC, CFB and OFB modes includes, in addition to the
plaintext, a 128-bit data block called the Initialization Vector (IV), which must be set in the Initialization
Vector Registers (INTVECTx). Additionally, the GCM mode 128-bit authentication data needs to be
programmed. The Initialization Vector is used in the initial step in the encryption of a message and in the
corresponding decryption of the message. The Initialization Vector Registers are also used by the
Counter mode to set the counter value.
It is necessary to notify AES module whenever the next data block it is going to process is the beginning
of a new message. This is done by writing a one to the New Message bit in the Control B register
(CTRLB.NEWMSG).
The AES modes of operation are selected by setting the AESMODE field in the Control A Register
(CTRLA.AESMODE). In Cipher Feedback Mode (CFB), five data sizes are possible (8, 16, 32, 64 or 128
bits), configurable by means of the CFBS field in the Control A Register (CTRLA.CFBS). In Counter
mode, the size of the block counter embedded in the module is 16 bits. Therefore, there is a rollover after
processing 1 megabyte of data. The data pre-processing, post-processing and data chaining for the
concerned modes are automatically performed by the module.
When data processing has completed, the Encryption Complete bit in the Interrupt Flag register
(INTFLAG.ENCCMP) is set by hardware (which triggers an interrupt request if the corresponding interrupt
is enabled). The processed output data is read out through the Output Data register (DATA) address from
the data buffer consisting of four 32-bit registers. The data buffer register that is read from when the next
read is performed is indicated by the Data Pointer field in the Data Buffer Pointer register
(DATABUFPTR). This field is incremented by one or wrapped by hardware when a read from the DATA
register address is performed. This field can also be programmed, giving the user direct control over
which output buffer register to read from. Note that when AES module is in the CFB operation mode with
the data segment size less than 128 bits, the output data must be read from the first (DATABUFPTR = 0)
and/or second (DATABUFPTR = 1) output buffer registers (see see
bit (INTFLAG.ENCCMP) is cleared by hardware after the processed data has been read from the relevant
output buffer registers.
Atmel SAM L22G / L22J / L22N [DATASHEET]
Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016
892
