This bus clock (CLK_DMAC_APB) is always synchronous to the module clock (CLK_DMAC_AHB), but
can be divided by a prescaler and may run even when the module clock is turned off.
Related Links
on page 145
26.5.4. DMA
Not applicable.
26.5.5. Interrupts
The interrupt request line is connected to the interrupt controller. Using the DMAC interrupt requires the
interrupt controller to be configured first.
Related Links
Nested Vector Interrupt Controller
on page 44
26.5.6. Events
The events are connected to the event system.
Related Links
26.5.7. Debug Operation
When the CPU is halted in debug mode the DMAC will halt normal operation. The DMAC can be forced to
continue operation during debugging. Refer to
26.5.8. Register Access Protection
All registers with write-access can be write-protected optionally by the Peripheral Access Controller
(PAC), except the following registers:
•
)
•
)
•
Channel Interrupt Flag Status and Clear register (
)
Optional write-protection by the Peripheral Access Controller (PAC) is denoted by the "PAC Write-
Protection" property in each individual register description.
PAC write-protection does not apply to accesses through an external debugger.
Related Links
PAC - Peripheral Access Controller
on page 50
26.5.9. Analog Connections
Not applicable.
26.6. Functional Description
26.6.1. Principle of Operation
The DMAC consists of a DMA module and a CRC module.
26.6.1.1. DMA
The DMAC can transfer data between memories and peripherals without interaction from the CPU. The
data transferred by the DMAC are called transactions, and these transactions can be split into smaller
data transfers. Figure 'DMA Transfer Sizes' shows the relationship between the different transfer sizes:
Atmel SAM L22G / L22J / L22N [DATASHEET]
Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016
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