Toshiba GR 200 Series, Instruction Manual

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6F2S1915 (0.46)
GRZ200 (Soft 031 & 032)
- 1079 -
10.2.6
Supervision of FPGA (FPGA error)
Detecting the error in the FPGA is achieved when the CPU module detects fatal failures.
(i)
Error level
The error level is set at level 1 (
Serious error 1
) for the supervision; checking errors on the
FPGA is carried out at any time. If the error is detected, the IED begins to restart its operation
automatically. Clearing the error message is made promptly when the error is cleared.
(ii)
Error message
When detecting an error, an error message can be shown on the LCD screen and an LED is lit.
Table 10.2-13 Error messages provided by the supervisor in CHK_FPGA
Message and level Meaning of the information
CP*_ (FPAG) error
Problem detected in the FPGA on the following module
instructed with “CP*_” as follows:
CP1M: CPU module
Error level Serious error (Level 1)
Table 10.2-14 Detailed information in Hexadecimal in CHK_FPGA
Display
area
Meaning of the detailed information
Left column Right column
Top
row
00000004: FPGA mode 00000008: FPAG interruption process
Middle
row
(No information displayed) (No information displayed)
Bottom
row
(No information is displayed) (No information is displayed)