CHAPTER 16 I
2
C BUS
User’s Manual U16896EJ2V0UD
462
16.2 Configuration
I
2
C0 includes the following hardware.
Table 16-1. Configuration of I
2
C0
Item Configuration
Registers
IIC shift register 0 (IIC0)
Slave address register 0 (SVA0)
Control registers
IIC control register 0 (IICC0)
IIC status register 0 (IICS0)
IIC flag register 0 (IICCF0)
IIC clock selection register 0 (IICCL0)
IIC function expansion register 0 (IICX0)
(1) IIC shift register 0 (IIC0)
The IIC0 register is used to convert 8-bit serial data to 8-bit parallel data and to convert 8-bit parallel data to 8-
bit serial data. The IIC0 register can be used for both transmission and reception.
Write and read operations to the IIC0 register are used to control the actual transmit and receive operations.
The IIC0 register can be read or written in 8-bit units.
Reset sets this register to 00H.
(2) Slave address register 0 (SVA0)
The SVA0 register sets local addresses when in slave mode.
The SVA0 register can be read or written in 8-bit units.
Reset sets this register to 00H.
(3) SO latch
The SO latch is used to retain the SDA0 pin’s output level.
(4) Wakeup controller
This circuit generates an interrupt request signal (INTIIC0) when the address received by this register matches
the address value set to the SVA0 register or when an extension code is received.
(5) Prescaler
This selects the sampling clock to be used.
(6) Serial clock counter
This counter counts the serial clocks that are output and the serial clocks that are input during transmit/receive
operations and is used to verify that 8-bit data was sent or received.
(7) Interrupt request signal generator
This circuit controls the generation of interrupt request signals (INTIIC0).
An I
2
C interrupt is generated by the following two triggers.
•
Falling edge of the eighth or ninth clock of the serial clock (set by IICC0.WTIM0 bit)
•
Interrupt request generated when a stop condition is detected (set by IICC0.SPIE0 bit)
