CHAPTER 15 CLOCKED SERIAL INTERFACE 0 (CSI0)
User’s Manual U16896EJ2V0UD
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(4) Cautions
To continue continuous transfers, it is necessary to either read the SIRBn register or write to the SOTBn
register during the transfer reservation period.
If access is performed to the SIRBn register or the SOTBn register when the transfer reservation period is
over, the following occurs.
(i) In case of conflict between transfer request clear and register access
Since transfer request clear has higher priority, the next transfer request is ignored. Therefore, transfer is
interrupted, and normal data transfer cannot be performed.
Figure 15-7. Transfer Request Clear and Register Access Conflict
SCK0n
(I/O)
INTCSI0n
signal
rq_clr
Reg_R/W
Transfer reservation period
Remarks 1.
rq_clr:
Internal signal. Transfer request clear signal.
Reg_R/W: Internal signal. This signal indicates that the SIRBn/SIRBnL register read or the
SOTBn/SOTBnL register write was performed.
2.
n = 0, 1