CHAPTER 3 CPU FUNCTIONS
User’s Manual U16896EJ2V0UD
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3.2.2 System register set
System registers control the status of the CPU and hold interrupt information.
Read from and write to system registers are performed by setting the system register numbers shown below with
the system register load/store instructions (LDSR, STSR instructions).
Table 3-2. System Register Numbers
Operand Specification Enabled
System
Register No.
System Register Name
LDSR
Instruction
STSR
Instruction
0
Interrupt status saving register (EIPC)
Note 1
Yes
Yes
1
Interrupt status saving register (EIPSW)
Note 1
Yes
Yes
2
NMI status saving register (FEPC)
Note 1
Yes
Yes
3
NMI status saving register (FEPSW)
Note 1
Yes
Yes
4
Interrupt source register (ECR)
No
Yes
5
Program status word (PSW)
Yes
Yes
6 to 15
Reserved numbers for future function expansion (The operation is not guaranteed
if accessed.)
No No
16
CALLT execution status saving register (CTPC)
Yes
Yes
17
CALLT execution status saving register (CTPSW)
Yes
Yes
18
Exception/debug trap status saving register (DBPC)
Yes
Note 2
Yes
Note 2
19
Exception/debug trap status saving register (DBPSW)
Yes
Note 2
Yes
Note 2
20
CALLT base pointer (CTBP)
Yes
Yes
21 to 31
Reserved numbers for future function expansion (The operation is not guaranteed
if accessed.)
No No
Notes 1.
Since only one set of these registers is available, the contents of this register must be saved by the
program when multiple interrupt servicing is enabled.
2.
These registers can be accessed only during the interval between the execution of the DBTRAP
instruction or illegal opcode and the DBRET instruction.
Caution Even if bit 0 of EIPC, FEPC, or CTPC is set (1) by the LDSR instruction, bit 0 is ignored during return
with the RETI instruction following interrupt servicing (because bit 0 of PC is fixed to 0). When
setting a value to EIPC, FEPC, and CTPC, set an even number (bit 0 = 0).
<R>
