CHAPTER 14 ASYNCHRONOUS SERIAL INTERFACE (UART)
User’s Manual U16896EJ2V0UD
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(4) Receive buffer register n (RXBn)
The RXBn register is an 8-bit buffer register for storing parallel data that had been converted by the receive
shift register.
When reception is enabled (ASIMn.RXEn bit = 1), receive data is transferred from the receive shift register to
the RXBn register, synchronized with the completion of the shift-in processing of one frame. Also, a reception
completion interrupt request signal (INTSRn) is generated by the transfer to the RXBn register. For
information about the timing for generating this interrupt request, refer to
14.5.4 Receive operation
.
If reception is disabled (ASIMn.RXEn bit = 0), the contents of the RXBn register are retained, and no
processing is performed for transferring data to the RXBn register even when the shift-in processing of one
frame is completed. Also, the INTSRn signal is not generated.
When 7 bits is specified for the data length, bits 6 to 0 of the RXBn register are transferred for the receive
data and the MSB (bit 7) is always 0. However, if an overrun error (ASISn.OVEn bit = 1) occurs, the receive
data at that time is not transferred to the RXBn register.
The RXBn register becomes FFH when a reset is input or ASIMn.UARTEn bit = 0.
This register is read-only in 8-bit units.
7
RXBn7
RXBn
(n = 0, 1)
6
RXBn6
5
RXBn5
4
RXBn4
3
RXBn3
2
RXBn2
1
RXBn1
0
RXBn0
After reset: FFH R Address: RXB0 FFFFFA02H, RXB1 FFFFFA12H