CHAPTER 16 I
2
C BUS
User’s Manual U16896EJ2V0UD
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(2/3)
EXC0
Detection of extension code reception
0
Extension code was not received.
1
Extension code was received.
Condition for clearing (EXC0 bit = 0)
Condition for setting (EXC0 bit = 1)
•
When a start condition is detected
•
When a stop condition is detected
•
Cleared by the LREL0 bit = 1 (exit from communications)
•
When the IICE0 bit changes from 1 to 0 (operation stop)
•
Reset
•
When the higher four bits of the received address data
is either “0000” or “1111” (set at the rising edge of the
eighth clock).
COI0
Detection of matching addresses
0
Addresses do not match.
1 Addresses
match.
Condition for clearing (COI0 bit = 0)
Condition for setting (COI0 bit = 1)
•
When a start condition is detected
•
When a stop condition is detected
•
Cleared by the LREL0 bit = 1 (exit from communications)
•
When the IICE0 bit changes from 1 to 0 (operation stop)
•
Reset
•
When the received address matches the local address
(SVA0 register) (set at the rising edge of the eighth
clock).
TRC0
Detection of transmit/receive status
0
Receive status (other than transmit status). The SDA0 line is set for high impedance.
1
Transmit status. The value in the SO latch is enabled for output to the SDA0 line (valid starting at the rising
edge of the first byte’s ninth clock).
Condition for clearing (TRC0 bit = 0)
Condition for setting (TRC0 bit = 1)
•
When a stop condition is detected
•
Cleared by the LREL0 bit = 1 (exit from communications)
•
When the IICE0 bit changes from 1 to 0 (operation stop)
•
Cleared by the IICC0.WREL0 bit = 1
Note
(wait release)
•
When the ALD0 bit changes from 0 to 1 (arbitration loss)
•
Reset
Master
•
When “1” is output to the first byte’s LSB (transfer
direction specification bit)
Slave
•
When a start condition is detected
When not used for communication
Master
•
When a start condition is generated
•
When “0” is output to the first byte’s LSB (transfer
direction specification bit)
Slave
•
When “1” is input in the first byte’s LSB (transfer
direction specification bit)
Note
The TRC0 bit is cleared to 0 and the SDA0 line becomes high impedance when the WREL0 bit is set
to 1 and wait state is released at the ninth clock with the TRC0 bit = 1.
<R>
