CHAPTER 16 I
2
C BUS
User’s Manual U16896EJ2V0UD
469
(2) IIC status register 0 (IICS0)
The IICS0 register indicates the status of the I
2
C0 bus.
The IICS0 register is read-only, in 8-bit or 1-bit units.
However, the IICS0 register can only be read when the IICC0.STT0 bit is 1 or during the wait period.
Reset sets this register to 00H.
Caution Accessing the IICS0 register is prohibited in the following statuses. For details, refer to 3.4.8
(1) (b) Access to special on-chip peripheral I/O register.
•
When the CPU operates on the subclock and the main clock oscillation is stopped
•
When the CPU operates on the internal oscillation clock
(1/3)
After reset: 00H
R
Address: FFFFFD86H
<7> <6> <5> <4> <3> <2> <1> <0>
IICS0 MSTS0 ALD0 EXC0 COI0 TRC0 ACKD0 STD0 SPD0
MSTS0
Master device status
0
Slave device status or communication standby status
1
Master device communication status
Condition for clearing (MSTS0 bit = 0)
Condition for setting (MSTS0 bit = 1)
•
When a stop condition is detected
•
When the ALD0 bit = 1 (arbitration loss)
•
Cleared by the IICC0.LREL0 bit = 1 (exit from
communications)
•
When the IICC0.IICE0 bit changes from 1 to 0 (operation
stop)
•
Reset
•
When a start condition is generated
ALD0
Detection of arbitration loss
0
This status means either that there was no arbitration or that the arbitration result was a “win”.
1
This status indicates the arbitration result was a “loss”. The MSTS0 bit is cleared to 0.
Condition for clearing (ALD0 bit = 0)
Condition for setting (ALD0 bit = 1)
•
Automatically cleared after the IICS0 register is read
Note
•
When the IICE0 bit changes from 1 to 0 (operation stop)
•
Reset
•
When the arbitration result is a “loss”.
Note
This bit is also cleared when a bit manipulation instruction is executed for another bit in IICS0.
<R>
<R>
