User’s Manual U16896EJ2V0UD
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CHAPTER 14 ASYNCHRONOUS SERIAL INTERFACE (UART)
In the V850ES/KE1+, two channels of asynchronous serial interface (UART) are provided. Of these channels,
UART0 supports LIN-bus.
14.1 Features
•
Maximum transfer speed: 312.5 kbps
•
Full-duplex
communications
On-chip RXBn register
On-chip TXBn register
•
Two-pin
configuration
Note
TXDn: Transmit data output pin
RXDn: Receive data input pin
•
Reception error detection functions
•
Parity
error
•
Framing
error
•
Overrun
error
•
Interrupt sources: 3 types
•
Reception error interrupt request signal (INTSREn):
Interrupt is generated according to the logical
OR of the three types of reception errors
•
Reception completion interrupt request signal (INTSRn):
Interrupt is generated when receive data is
transferred from the receive shift register to
the RXBn register after serial transfer is
completed during a reception enabled state
•
Transmission completion interrupt request signal (INTSTn): Interrupt is generated when the serial
transmission of transmit data (8 or 7 bits) from
the transmit shift register is completed
•
Character length: 7 or 8 bits
•
Parity functions: Odd, even, 0, or none
•
Transmission stop bits: 1 or 2 bits
•
MSB-first or LSB-first transfer of data selectable (UART0 only)
•
Transmit data output level inversion function (UART0 only)
•
13 to 20 bits selectable for Sync Break Field transmission (UART0 only)
•
11 bits or more identifiable for Sync Break Field reception (SBF reception flag (UART0 only))
•
On-chip dedicated baud rate generator
Note
The ASCK0 pin (external clock input) is available only for UART0.
Remark
n = 0, 1
