CHAPTER 16 I
2
C BUS
User’s Manual U16896EJ2V0UD
478
16.5 I
2
C Bus Definitions and Control Methods
The following section describes the I
2
C bus’s serial data communication format and the status generated by the I
2
C
bus. The transfer timing for the “start condition”, “address”, “transfer direction specification”, “data”, and “stop
condition” generated via the I
2
C bus’s serial data bus is shown below.
Figure 16-4. I
2
C Bus’s Serial Data Transfer Timing
1 to 7
8
9
1 to 8
9
1 to 8
9
SCL0
SDA0
Start
condition
Address
R/W
ACK
Data
Data
Stop
condition
ACK
ACK
The master device generates the start condition, slave address, and stop condition.
ACK can be generated by either the master or slave device (normally, it is generated by the device that receives 8-
bit data).
The serial clock (SCL0) is continuously output by the master device. However, in the slave device, the SCL0 pin’s
low-level period can be extended and a wait can be inserted.
16.5.1 Start condition
A start condition is met when the SCL0 pin is at high level and the SDA0 pin changes from high level to low level.
The start conditions for the SCL0 pin and SDA0 pin are generated when the master device starts a serial transfer to
the slave device. Start conditions can be detected when the device is used as a slave.
Figure 16-5. Start Conditions
H
SCL0
SDA0
A start condition is generated when the IICC0.STT0 bit is set to 1 after a stop condition has been detected
(IICS0.SPD0 bit = 1). When a start condition is detected, IICS0.STD0 bit is set to 1.
