CHAPTER 11 WATCHDOG TIMER FUNCTIONS
User’s Manual U16896EJ2V0UD
350
(2) Watchdog timer mode register 1 (WDTM1)
This register sets the watchdog timer 1 operation mode and enables/disables count operations.
This register is a special register that can be written only in a special sequence (refer to
3.4.7 Special
registers
).
The WDTM1 register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
Caution Accessing the WDTM1 register is prohibited in the following statuses. For details, refer to
3.4.8 (1) (b) Access to special on-chip peripheral I/O register.
•
When the CPU operates on the subclock and the main clock oscillation is stopped
•
When the CPU operates on the internal oscillation clock
RUN1
Stop counting
Clear counter and start counting
RUN1
0
1
Selection of operation mode of watchdog timer 1
Note 1
WDTM1
0
0
WDTM14 WDTM13
0
0
0
After reset: 00H R/W Address: FFFFF6C2H
Interval timer mode
(Upon overflow, maskable interrupt INTWDTM1 is generated.)
Watchdog timer mode 1
Note 3
(Upon overflow, non-maskable interrupt INTWDT1 is generated.)
Watchdog timer mode 2
(Upon overflow, reset operation WDTRES1 is started.)
WDTM14
0
0
1
1
WDTM13
0
1
0
1
Selection of operation mode of watchdog timer 1
Note 2
< >
Notes 1.
Once the RUN1 bit is set (to 1), it cannot be cleared (to 0) by software.
Therefore, when counting is started, it cannot be stopped except by reset.
2.
Once the WDTM13 and WDTM14 bits are set (to 1), they cannot be cleared (to 0) by software and
can be cleared only by reset.
3.
For non-maskable interrupt servicing due to non-maskable interrupt request signal (INTWDT1),
refer to
17.10 Cautions
.
<R>
