CHAPTER 16 I
2
C BUS
User’s Manual U16896EJ2V0UD
468
(4/4)
SPT0
Stop condition trigger
0
Stop condition is not generated.
1
Stop condition is generated (termination of master device’s transfer).
After the SDA0 line goes to low level, either set the SCL0 line to high level or wait until the SCL0 pin
goes to high level. Next, after the rated amount of time has elapsed, the SDA0 line is changed from
low level to high level and a stop condition is generated.
Cautions concerning set timing
For master reception:
Cannot be set to 1 during transfer. Can be set to 1 only when the ACKE0 bit has
been cleared to 0 and during the wait period after slave has been notified of final
reception.
For master transmission: A stop condition may not be generated normally during the acknowledgment period.
Set to 1 during the wait period that follows output of the ninth clock.
•
Cannot be set to 1 at the same time as the STT0 bit.
•
The SPT0 bit can be set to 1 only when in master mode
Note
.
•
When the WTIM0 bit has been cleared to 0, if the SPT0 bit is set to 1 during the wait period that follows output
of eight clocks, note that a stop condition will be generated during the high-level period of the ninth clock.
The WTIM0 bit should be changed from 0 to 1 during the wait period following output of eight clocks, and the
SPT0 bit should be set to 1 during the wait period that follows output of the ninth clock.
•
When the SPT0 bit is set to 1, setting the SPT0 bit to 1 again is disabled until the setting is cleared to 0.
Condition for clearing (SPT0 bit = 0)
Condition for setting (SPT0 bit = 1)
•
Cleared by loss in arbitration
•
Automatically cleared after stop condition is detected
•
When the LREL0 bit = 1 (exit from communications)
•
When the IICE0 bit changes from 1 to 0 (operation stop)
•
Reset
•
Set by instruction
Note
Set the SPT0 bit to 1 only in master mode. However, the SPT0 bit must be set to 1 and a stop
condition generated before the first stop condition is detected following the switch to operation enable
status. For details, refer to
16.14 Cautions
.
Caution When the IICS0.TRC0 bit is set to 1, the WREL0 bit is set to 1 during the ninth clock and wait
is canceled, after which the TRC0 bit is cleared to 0 and the SDA0 line is set to high
impedance.
Remark
The SPT0 bit is 0 if it is read after data setting.
