![background image](http://html1.mh-extra.com/html/omron/sysmac-cs1d-cpu/sysmac-cs1d-cpu_reference-manual_742268286.webp)
247
Timer and Counter Instructions
Section 3-6
Description
When the timer input is OFF, the timer specified by N is reset, i.e., the timer’s
PV is reset to the SV and its Completion Flag is turned OFF.
When the timer input goes from OFF to ON, TIM/TIMX(550) starts decrement-
ing the PV. The PV will continue timing down as long as the timer input
remains ON and the timer’s Completion Flag will be turned ON when the PV
reaches 0000.
The status of the timer’s PV and Completion Flag will be maintained after the
timer times out. To restart the timer, the timer input must be turned OFF and
then ON again or the timer’s PV must be changed to a non-zero value (by
MOV(021), for example).
The following timing chart shows the behavior of the timer’s PV and Comple-
tion Flag when the timer input is turned OFF before the timer times out.
Indirect DM/EM
addresses in binary
---
@ D00000 to @ D32767
@ E00000 to @ E32767
@ En_00000 to
@ En_32767
(n = 0 to C)
Indirect DM/EM
addresses in BCD
---
*D00000 to *D32767
*E00000 to *E32767
*En_00000 to *En_032767
(n = 0 to C)
Constants
---
BCD:
#0000 to 9999 (BCD)
“&” cannot be used.
Binary:
&0 to &65535 (decimal)
#0000 to #FFFF (hex)
Data Registers
---
DR0 to DR15
Index Registers
---
---
Indirect addressing
using Index Registers
,IR0 to ,IR15
–2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
Area
N
S
SV
Timer input
Timer PV
Completion
Flag
SV
Timer input
Timer PV
Completion
Flag
Summary of Contents for SYSMAC CS1D-CPU**
Page 3: ...iv...
Page 29: ...xxx...
Page 185: ...146 List of Instructions by Function Code Section 2 4...
Page 1389: ...1350 CJ series Instruction Execution Times and Number of Steps Section 4 2...
Page 1390: ...1351 Appendix A ASCII Code Table ASCII SP Four leftmost bits Four rightmost bits...
Page 1391: ...1352 ASCII Code Table Appendix A...