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550
Logic Instructions
Section 3-13
Description
ANDW(034) takes the logical AND of data specified in I
1
and I
2
and outputs
the result to R.
• The logical AND is taken of corresponding bits in I
1
and I
2
in succession.
• When the content of corresponding bits in both I
1
and I
2
are 1 or when
either is 0, a 0 will be output to the corresponding bit in R.
I
1
, I
2
→
R
Flags
Precautions
When ANDW(034) is executed, the Error Flag will turn OFF.
If as a result of the AND, the content of R is 0000 hex, the Equals Flag will
turn ON.
If as a result of the AND, the leftmost bit of R is 1, the Negative Flag will turn
ON.
Indirect DM/EM
addresses in binary
@ D00000 to @ D32767
@ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM
addresses in BCD
*D00000 to *D32767
*E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants
#0000 to #FFFF
(binary)
---
Data Registers
DR0 to DR15
Index Registers
---
Indirect addressing
using Index Registers
,IR0 to ,IR15
–2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15
Area
I
1
I
2
R
I
1
I
2
R
1
1
1
1
0
0
0
1
0
0
0
0
Name
Label
Operation
Error Flag
ER
OFF
Equals Flag
=
ON when the result is 0.
OFF in all other cases.
Negative Flag
N
ON when the leftmost bit of R is 1.
OFF in all other cases.
Summary of Contents for SYSMAC CS1D-CPU**
Page 3: ...iv...
Page 29: ...xxx...
Page 185: ...146 List of Instructions by Function Code Section 2 4...
Page 1389: ...1350 CJ series Instruction Execution Times and Number of Steps Section 4 2...
Page 1390: ...1351 Appendix A ASCII Code Table ASCII SP Four leftmost bits Four rightmost bits...
Page 1391: ...1352 ASCII Code Table Appendix A...