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208
Sequence Control Instructions
Section 3-5
Precautions
NOP(000) can only be used with mnemonic displays, not with ladder pro-
grams.
3-5-3
Overview of Interlock Instructions
Interlock Instructions
The following instruction combinations can be used to interlock outputs in a
program section.
• INTERLOCK and INTERLOCK CLEAR (IL(002) and IL(003))
• MULTI-INTERLOCK DIFFERENTIATION HOLD and MULTI-INTERLOCK
CLEAR (MILH(517) and MILC(519))*
Note
MILH(517) holds the status of the Differentiation Flag, so differentiat-
ed instructions that were interlocked are executed after the interlock
is cleared.
• MULTI-INTERLOCK DIFFERENTIATION RELEASE and MULTI-INTER-
LOCK CLEAR (MILR(518) and MILC(519))*
Note
MILR(518) does not hold the status of the Differentiation Flag, so dif-
ferentiated instructions that were interlocked are not executed after
the interlock is cleared.
* These instructions are supported only by CS/CJ-series CPU Unit Ver. 2.0
or later.
Differences between
Interlocks and Multiple
Interlocks
Regular interlocks (IL(002) and IL(003)) cannot be nested, but multiple inter-
locks (MILH(517), MILR(518), and MILC(519)) can be nested. Ladder pro-
gramming can be simplified by nesting multiple interlocks, as shown in the
following diagram.
a
MILH
0
A1
b
MILH
1
A2
c
MILH
2
A3
MILC
2
MILC
1
MILC
0
a
IL
A1
ILC
a
IL
A2
b
b
c
ILC
a
IL
A3
ILC
Interlocks with MILH and MILC
Interlocks with IL and ILC
Summary of Contents for SYSMAC CS1D-CPU**
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Page 29: ...xxx...
Page 185: ...146 List of Instructions by Function Code Section 2 4...
Page 1389: ...1350 CJ series Instruction Execution Times and Number of Steps Section 4 2...
Page 1390: ...1351 Appendix A ASCII Code Table ASCII SP Four leftmost bits Four rightmost bits...
Page 1391: ...1352 ASCII Code Table Appendix A...