1176
Other Instructions
Section 3-31
Ladder Symbol
Variations
Applicable Program Areas
Description
When the execution condition is ON, FRMCV(284) executes the following
operations.
1.
The CV-series PLC memory address specified in S is converted to its
equivalent CV-series data area address.
2.
FRMCV(284) determines the CS/CJ-series PLC memory address that cor-
responds to the same CV-series data area address.
3.
The CS/CJ-series PLC memory address is output to D. (An index register
(IR0 to IR15) must be specified for D.)
The following example shows FRMCV(284) used to convert the CV-series
PLC memory address for D00001.
FRMCV(284)
S
D
S: Word containing the CV-
series PLC memory address
D: Destination Index Register
Variations
Executed Each Cycle for ON Condition
FRMCV(284)
Executed Once for Upward Differentiation
@FRMCV(284)
Executed Once for Downward Differentiation
Not supported.
Immediate Refreshing Specification
Not supported.
Block program areas
Step program areas
Subroutines
Interrupt tasks
OK
OK
OK
OK
FRMCV
D00000
IR1
#2001
D00000
2001 Hex
D00001
D00001
10001 Hex
IR1
10001 Hex
1. The CV-series PLC memory address is
converted to its equivalent CV-series data
area address.
CV-series PLC
memory address
CV-series data
area address
CS/CJ-series data
area address
CS/CJ-series
PLC memory
2. The corresponding CV-series data area
address is converted to its CS/CJ-series
PLC memory address.
Storage
3. The CS/CJ-series PLC memory
address is stored in D.
Summary of Contents for SYSMAC CS1D-CPU**
Page 3: ...iv...
Page 29: ...xxx...
Page 185: ...146 List of Instructions by Function Code Section 2 4...
Page 1389: ...1350 CJ series Instruction Execution Times and Number of Steps Section 4 2...
Page 1390: ...1351 Appendix A ASCII Code Table ASCII SP Four leftmost bits Four rightmost bits...
Page 1391: ...1352 ASCII Code Table Appendix A...