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169
Sequence Input Instructions
Section 3-3
3-3-5
OR: OR
Purpose
Takes a logical OR of the ON/OFF status of the specified operand bit and the
current execution condition.
Ladder Symbol
Variations
Note
Immediate refreshing is not supported by CS1D CPU Units for Duplex-CPU
Systems.
Applicable Program Areas
Operand Specifications
OR LD
---
AND LD
---
OUT
000006
Instruction
Operand
Bus bar
Variations
Creates ON Each Cycle OR Result is ON
OR
Creates ON Once for Upward Differentiation
@OR
Creates ON Once for Downward Differentiation
%OR
Immediate Refreshing Specification (See note.)
!OR
Combined
Variations
Refreshes Input Bit and Creates ON Once for
Upward Differentiation (See note.)
!@OR
Refreshes Input Bit and Creates ON Once for
Downward Differentiation (See note.)
!%OR
Block program areas
Step program areas
Subroutines
Interrupt tasks
OK
OK
OK
OK
Area
OR bit operand
CIO Area
CIO 000000 to CIO 614315
Work Area
W00000 to W51115
Holding Bit Area
H00000 to H51115
Auxiliary Bit Area
A00000 to A95915
Timer Area
T0000 to T4095
Counter Area
C0000 to C4095
Task Flag Area
TK0000 to TK0031
Condition Flags
ER, CY, N, OF, UF, >, =, <, >=, <>, <=, ON, OFF, AER
Clock Pulses
0.02 s, 0.1 s, 0.2 s, 1 s, 1 min
DM Area
---
EM Area without bank
---
EM Area with bank
---
Indirect DM/EM
addresses in binary
---
Indirect DM/EM
addresses in BCD
---
Constants
---
Data Registers
---
Summary of Contents for SYSMAC CS1D-CPU**
Page 3: ...iv...
Page 29: ...xxx...
Page 185: ...146 List of Instructions by Function Code Section 2 4...
Page 1389: ...1350 CJ series Instruction Execution Times and Number of Steps Section 4 2...
Page 1390: ...1351 Appendix A ASCII Code Table ASCII SP Four leftmost bits Four rightmost bits...
Page 1391: ...1352 ASCII Code Table Appendix A...