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268
Timer and Counter Instructions
Section 3-6
Applicable Program Areas
Operands
D1: Completion Flag
Bit 0 of D1 acts as the Completion Flag for TIML(542)/TIMLX(553).
D2: PV Word
D2+1 and D2 contain the 8-digit binary or BCD PV. (D2 and D2+1 must be in
the same data area.) The PV can range from #00000000 to #99999999 for
TIML(542) and &00000000 to &4294967294 (decimal) or #00000000 to
#FFFFFFFF (hexadecimal) for TIMLX(553).
S: SV Word
S+1 and S contain the 8-digit binary or BCD SV. (S and S+1 must be in the
same data area.) The SV must be between #00000000 to #99999999 for
TIML(542) and &00000000 to &4294967294 (decimal) or #00000000 to
#FFFFFFFF (hexadecimal) for TIMLX(553).
Operand Specifications
Block program areas
Step program areas
Subroutines
Interrupt tasks
Not allowed
OK
OK
Not allowed
15
D1
0
Completion Flag
Do not use.
D2
D2+1
D2
S
S+1
S
Area
D1
D2
S
CIO Area
CIO 0000 to
CIO 6143
CIO 0000 to CIO 6142
Work Area
W000 to W511
W000 to W510
Holding Bit Area
H000 to H511
H000 to H510
Auxiliary Bit Area
A448 to A959
A448 to A958
A000 to A958
Timer Area
---
---
T0000 to T4094
Counter Area
---
---
C0000 to C4094
DM Area
D00000 to
D32767
D00000 to D32766
EM Area without bank
E00000 to
E32767
E00000 to E32766
EM Area with bank
En_00000 to
En_32767
(n = 0 to C)
En_00000 to En_32766
(n = 0 to C)
Indirect DM/EM
addresses in binary
@ D00000 to @ D32767
@ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM
addresses in BCD
*D00000 to *D32767
*E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Summary of Contents for SYSMAC CS1D-CPU**
Page 3: ...iv...
Page 29: ...xxx...
Page 185: ...146 List of Instructions by Function Code Section 2 4...
Page 1389: ...1350 CJ series Instruction Execution Times and Number of Steps Section 4 2...
Page 1390: ...1351 Appendix A ASCII Code Table ASCII SP Four leftmost bits Four rightmost bits...
Page 1391: ...1352 ASCII Code Table Appendix A...