![background image](http://html1.mh-extra.com/html/omron/sysmac-cs1d-cpu/sysmac-cs1d-cpu_reference-manual_742268329.webp)
290
Timer and Counter Instructions
Section 3-6
IR0 contains the PLC memory address of the timer PV and IR1 contains the
PLC memory address of the timer Completion Flag.
1,2,3...
1.
MOVRW(561) moves the PLC memory address of the PV for timer T0000
to IR0. Afterwards IR0 can be used in place of the timer number.
2.
MOVR(560) moves the PLC memory address of the Completion Flag for
timer T0000 to IR1.
3.
MOVR(560) moves the PLC memory address of CIO 200000 into IR2.
4.
MOV(021) moves &100 into D00000 for indirect addressing of the timer
SVs.
5.
The content of IR0, IR1, IR2, and D00000 are incremented by 1 each time
as this loop is executed 100 times, starting timers T0000 through T0099.
DM address
Content
Function
D00100
0010
SV for T0000
D00101
0100
SV for T0001
D00102
0050
SV for T0002
.
.
.
.
.
.
.
.
.
D00199
0999
SV for T0099
1
2
3
4
5
P_On
P_On
&100
FOR
&100
@D00000
++
NEXT
(Always ON
Flag)
(Always ON
Flag)
Summary of Contents for SYSMAC CS1D-CPU**
Page 3: ...iv...
Page 29: ...xxx...
Page 185: ...146 List of Instructions by Function Code Section 2 4...
Page 1389: ...1350 CJ series Instruction Execution Times and Number of Steps Section 4 2...
Page 1390: ...1351 Appendix A ASCII Code Table ASCII SP Four leftmost bits Four rightmost bits...
Page 1391: ...1352 ASCII Code Table Appendix A...