![background image](http://html1.mh-extra.com/html/omron/sysmac-cs1d-cpu/sysmac-cs1d-cpu_reference-manual_742268076.webp)
37
Instruction Functions
Section 2-2
MULTI-OUTPUT
TIMER
MTIM
543
(BCD)
MTIMX
554
(Binary)
(CS1-H, CJ1-H,
CJ1M, or CS1D
only)
Output
Required
270
COUNTER
CNT
(BCD)
CNTX
546
(Binary)
(CS1-H, CJ1-H,
CJ1M, or CS1D
only)
Output
Required
276
Instruction
Mnemonic
Code
Symbol/Operand
Function
Location
Execution
condition
Page
MTIM(543)
D1
D2
S
D1
:
Completion
Flags
D2
:
PV word
S
:
1st SV word
SV 7
SV 2
SV 1
SV 0
0
to
to
Timer input
Timer PV (D2)
to
Bit 7
to
Timer PV
Timer SVs
0
Bit 2
Bit 1
Bit 0
MTIM(543)/MTIMX(554) operates a 0.1-s incrementing timer with 8
independent SVs and Completion Flags. The setting range for the
set value (SV) is 0 to 999.9 s for BCD and 0 to 6,553.5 s for binary
(decimal or hexadecimal).
Completion
Flags (D1)
MTIMX(554)
D1
D2
S
D1
:
Completion
Flags
D2
:
PV word
S
:
1st SV word
CNT
N
S
Count
input
Reset
input
N
:
Counter
number
S
:
Set value
SV
Count input
Counter PV
Completion
Flag
Reset input
CNT/CNTX(546) operates a decrementing counter. The setting range
for the set value (SV) is 0 to 9,999 for BCD and 0 to 65,535 for binary
(decimal or hexadecimal).
CNTX(546)
N
S
Count
input
Reset
input
N
:
Counter
number
S
:
Set value
Summary of Contents for SYSMAC CS1D-CPU**
Page 3: ...iv...
Page 29: ...xxx...
Page 185: ...146 List of Instructions by Function Code Section 2 4...
Page 1389: ...1350 CJ series Instruction Execution Times and Number of Steps Section 4 2...
Page 1390: ...1351 Appendix A ASCII Code Table ASCII SP Four leftmost bits Four rightmost bits...
Page 1391: ...1352 ASCII Code Table Appendix A...