![background image](http://html1.mh-extra.com/html/omron/sysmac-cs1d-cpu/sysmac-cs1d-cpu_reference-manual_742268258.webp)
219
Sequence Control Instructions
Section 3-5
• Operation of Differentiated Instructions in an MILH(517) Interlock
If there is a differentiated instruction (DIFU, DIFD, or instruction with a @
or % prefix) between MILH(517) and the corresponding MILC(519), that in-
struction
will
be executed after the interlock is cleared if the differentiation
condition of the instruction was established. (The system compares the ex-
ecution condition’s status when the interlock started to its status when the
interlock was cleared.)
In the same way, a differentiated instruction will be executed if its execution
condition is established at the same time that the interlock is started or
cleared.
Many other conditions in the program may cause the differentiation condi-
tion to be reset even if it was established during the interlock. In this case,
the differentiation instruction will not be executed when the interlock is
cleared.
• Example
When a DIFFERENTIATE UP (DIFU(013)) instruction is being used
and the input condition is OFF when the interlock starts and ON when
the interlock is cleared, DIFU(013)
will
be executed when the interlock
is cleared. (Differentiated instructions operate the same in the
MILH(517) interlock as they would in an IL(002) interlock.)
Instruction
Operation of Differentiated Instructions
MILH(517)
MULTI-INTERLOCK DIFFER-
ENTIATION HOLD
A differentiated instruction (DIFU, DIFD, or
instruction with a @ or % prefix)
will
be exe-
cuted after the interlock is cleared if the differ-
entiation condition of the instruction was
established while the instruction was inter-
locked. (The status of the execution condition
when the interlock started is compared to its
status when the interlock was cleared.)
MILR(518)
MULTI-INTERLOCK DIFFER-
ENTIATION RELEASE
A differentiated instruction (DIFU, DIFD, or
instruction with a @ or % prefix)
will not
be
executed after the interlock is cleared even if
the differentiation condition of the instruction
was established while the instruction was inter-
locked.
MILH
0
MILC
0
DIFU
001000
000000
000001
1. When CIO 000000 is OFF (interlock starts), the DIFU's CIO 000001 input condition is OFF.
2. The DIFU's CIO 000001 input condition goes from OFF to ON while CIO 000000 is OFF (DIFU interlocked),
3. When CIO 000000 goes from OFF to ON (interlock cleared), DIFU is executed if CIO 000001 is still ON.
Summary of Contents for SYSMAC CS1D-CPU**
Page 3: ...iv...
Page 29: ...xxx...
Page 185: ...146 List of Instructions by Function Code Section 2 4...
Page 1389: ...1350 CJ series Instruction Execution Times and Number of Steps Section 4 2...
Page 1390: ...1351 Appendix A ASCII Code Table ASCII SP Four leftmost bits Four rightmost bits...
Page 1391: ...1352 ASCII Code Table Appendix A...