671
Double-precision Floating-point Instructions (CS1-H, CJ1-H, CJ1M, or CS1D Only)
Section 3-16
Description
/D(848) divides the double-precision (64-bit) floating-point number in words
Dd to Dd+3 by the double-precision (64-bit) floating-point number in words Dr
to Dr+3 and places the result in words D to D+3. (The floating point data must
be in IEEE754 format.)
If the absolute value of the result is greater than the maximum value that can
be expressed as floating-point data, the Overflow Flag will turn ON and the
result will be output as
±∞
.
If the absolute value of the result is less than the minimum value that can be
expressed as floating-point data, the Underflow Flag will turn ON and the
result will be output as 0.
The various combinations of dividend and divisor data will produce the results
shown in the following table.
Note
1.
The results could be zero (including underflows), a numeral, +
∞
, or –
∞
.
2.
The results will be zero for underflows.
3.
The Error Flag will be turned ON and the instruction will not be executed.
EM Area without bank
E00000 to E32764
EM Area with bank
En_00000 to En_32764
(n = 0 to C)
Indirect DM/EM
addresses in binary
@ D00000 to @ D32767
@ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM
addresses in BCD
*D00000 to *D32767
*E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants
---
Data Registers
---
Index Registers
---
Indirect addressing
using Index Registers
,IR0 to ,IR15
–2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15
Area
Dd
Dr
D
Dividend
Divisor
0
Numeral
+
∞
–
∞
NaN
0
See note 3.
+/–
∞
+
∞
–
∞
Numeral
0
See note 1.
+/–
∞
+/–
∞
+
∞
0
See note 2.
See note 3.
See note 3.
–
∞
0
See note 2.
See note 3.
See note 3.
NaN
See note 3.
S1+1
S2+1
÷
S1
S2
D+1
DCH
S1+2
S2+2
D+2
S1+3
S2+3
D+3
Result (floating-point data, 64-bits)
Divisor (floating-point data, 64-bits)
Dividend (floating-point data, 64-bits)
Summary of Contents for SYSMAC CS1D-CPU**
Page 3: ...iv...
Page 29: ...xxx...
Page 185: ...146 List of Instructions by Function Code Section 2 4...
Page 1389: ...1350 CJ series Instruction Execution Times and Number of Steps Section 4 2...
Page 1390: ...1351 Appendix A ASCII Code Table ASCII SP Four leftmost bits Four rightmost bits...
Page 1391: ...1352 ASCII Code Table Appendix A...