![background image](http://html1.mh-extra.com/html/omron/sysmac-cs1d-cpu/sysmac-cs1d-cpu_reference-manual_742268461.webp)
422
Increment/Decrement Instructions
Section 3-10
3-10-7 DECREMENT BCD: – –B(596)
Purpose
Decrements the 4-digit BCD content of the specified word by 1.
Ladder Symbol
Variations
Applicable Program Areas
Operand Specifications
Description
The – –B(596) instruction subtracts 1 from the BCD content of Wd. The spec-
ified word will be decremented by 1 every cycle as long as the execution con-
dition of – –B(596) is ON. When the up-differentiated variation of this
instruction (@– –B(596)) is used, the specified word is decremented only
when the execution condition has gone from OFF to ON.
− −
B(596)
Wd
Wd
:
Word
Variations
Executed Each Cycle for ON Condition
– –B(596)
Executed Once for Upward Differentiation
@– –B(596)
Executed Once for Downward Differentiation
Not supported
Immediate Refreshing Specification
Not supported
Block program areas
Step program areas
Subroutines
Interrupt tasks
OK
OK
OK
OK
Area
Wd
CIO Area
CIO 0000 to CIO 6143
Work Area
W000 to W511
Holding Bit Area
H000 to H511
Auxiliary Bit Area
A448 to A959
Timer Area
T0000 to T4095
Counter Area
C0000 to C4095
DM Area
D00000 to D32767
EM Area without bank
E00000 to E32767
EM Area with bank
En_00000 to En_32767
(n = 0 to C)
Indirect DM/EM
addresses in BCD
@ D00000 to @ D32767
@ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM
addresses in BCD
*D00000 to *D32767
*E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants
---
Data Registers
DR0 to DR15
Index Registers
---
Indirect addressing
using Index Registers
,IR0 to ,IR15
–2048 to +2047, IR0 to –2048 to +2047, IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15
Summary of Contents for SYSMAC CS1D-CPU**
Page 3: ...iv...
Page 29: ...xxx...
Page 185: ...146 List of Instructions by Function Code Section 2 4...
Page 1389: ...1350 CJ series Instruction Execution Times and Number of Steps Section 4 2...
Page 1390: ...1351 Appendix A ASCII Code Table ASCII SP Four leftmost bits Four rightmost bits...
Page 1391: ...1352 ASCII Code Table Appendix A...