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226
Sequence Control Instructions
Section 3-5
If there is an ILC(003) instruction between an MILR(518) and MILC(519) pair,
the ILC(003) instruction will be ignored and the full program section between
MILR(518) and MILC(519) will be interlocked.
If there is another MILH(517) or MILR(518) instruction with the same interlock
number between an MILH(517) and MILC(519) pair and the first MILH(517)
instruction’s interlock is engaged, the second MILH(517)/MILR(518) will not
operate.
If there is another MILH(517) or MILR(518) instruction with the same interlock
number between an MILH(517) and MILC(519) pair and the first MILH(517)
instruction’s interlock is not engaged, the second MILH(517)/MILR(518) will
operate normally.
Note
The MILR(518) interlocks operate in the same way if there is another
MILH(517) or MILR(518) instruction with the same interlock number between
an MILR(518) and MILC(519) pair.
If there is an MILC(519) instruction with a different interlock number between
an MILH(517)/MILR(518) and MILC(519) pair, that MILC(519) instruction will
be ignored.
a
MILR
0
MILC
0
A1
ILC
A2
The ILC(003) instruction is ignored.
When input condition "a" is OFF, program
sections A1 and A2 are interlocked.
a
MILH
0
MILC
0
A1
b
MILH
0
A2
When input condition "a" is OFF, program
sections A1 and A2 are both interlocked,
even if input condition "b" is ON.
When input condition "a" is ON and "b"
is OFF, only program section A2 is
interlocked.
Summary of Contents for SYSMAC CS1D-CPU**
Page 3: ...iv...
Page 29: ...xxx...
Page 185: ...146 List of Instructions by Function Code Section 2 4...
Page 1389: ...1350 CJ series Instruction Execution Times and Number of Steps Section 4 2...
Page 1390: ...1351 Appendix A ASCII Code Table ASCII SP Four leftmost bits Four rightmost bits...
Page 1391: ...1352 ASCII Code Table Appendix A...