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194
Sequence Output Instructions
Section 3-4
Description
When the execution condition goes from OFF to ON, DIFU(013) turns B ON.
When DIFU(013) is reached in the next cycle, B is turned OFF.
When the execution condition goes from ON to OFF, DIFD(014) turns B ON.
When DIFD(014) is reached in the next cycle, B is turned OFF.
DIFU(013) and DIFD(014) have immediate refreshing variations (!DIFU(013)
and !DIFD(014)). When an external output bit has been specified for B in one
of these instructions, any changes to B will be refreshed when the instruction
is executed and reflected immediately in the output bit. (The changes will not
be reflected immediately if the bit is allocated to a Group-2 High-density I/O
Unit, High-density Special I/O Unit, or a Unit mounted in a SYSMAC BUS
Remote I/O Slave Rack.)
UP(521) and DOWN(522) can be used to execute an instruction for just one
cycle when the execution condition goes from OFF
→
ON or ON
→
OFF.
Refer to
3-3-13 CONDITION ON/OFF: UP(521) and DOWN(522)
for details.
Flags
No flags are affected by DIFU(013) and DIFD(014).
Precautions
The operation of DIFU(013) or DIFD(014) depends on the execution condition
for the instruction itself as well as the execution condition for the program sec-
tion when it is programmed in an interlocked program section, a jumped pro-
gram section, or a subroutine. Refer to
3-5-4 INTERLOCK and INTERLOCK
CLEAR: IL(002) and ILC(003), 3-5-6 JUMP and JUMP END: JMP(004) and
JME(005)
, and
3-20 Interrupt Control Instructions
for details.
If DIFU(013) is used in a FOR-NEXT loop and the loop repeats in a cycle, the
controlled bit will be always ON or always OFF within that loop.
Index Registers
---
Indirect addressing
using Index Registers
,IR0 to ,IR15
–2048 to +2047, IR0 to –2048 to +2047, IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –) IR0 to ,15–(– –) IR
Area
B
Status of B
1 cycle
Execution condition
Status of B
1 cycle
Execution condition
Summary of Contents for SYSMAC CS1D-CPU**
Page 3: ...iv...
Page 29: ...xxx...
Page 185: ...146 List of Instructions by Function Code Section 2 4...
Page 1389: ...1350 CJ series Instruction Execution Times and Number of Steps Section 4 2...
Page 1390: ...1351 Appendix A ASCII Code Table ASCII SP Four leftmost bits Four rightmost bits...
Page 1391: ...1352 ASCII Code Table Appendix A...