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Interrupt Control Instructions
Section 3-20
sponding bit of C is ON and retains the recorded interrupt input when the cor-
responding bit is OFF.
If an I/O interrupt task is being executed and an interrupt input with a different
interrupt number is received, that interrupt number is recorded internally. The
recorded I/O interrupts are executed later in order of their priority (from the
lowest number to the highest).
If you want to ignore interrupt inputs that are received while an interrupt task is
being executed, use CLI(691) to clear the recorded interrupts before they are
executed.
N = 4 or 5: Setting the Time to the First Scheduled Interrupt Task
When N is 4 or 5, the content of C specifies the time interval to the first sched-
uled interrupt task.
Note
1.
The CJ1M-CPU11/21 supports only one scheduled interrupt task, interrupt
task 2 for scheduled interrupt 0.
2.
The time unit for the scheduled interrupt tasks is set in the PLC Setup as
the Scheduled Interrupt Interval.
■
N = 10 or 11: Clearing High-speed Counter Interrupts (CJ1M Only)
When N is 10 or 11, CLI(691) clears or retains the recorded high-speed
counter interrupt (either target or range comparison) specified by N.
Flags
Interrupts have different priority levels. A power OFF interrupt is given the
highest priority, followed by I/O interrupts, external interrupts, and finally
scheduled interrupts. Lower numbered I/O interrupts are given priority over a
higher numbered I/O interrupts.
Operation Examples
Example for CS1W-INT01/CJ1W-INT01
When CIO 000000 is ON in the following example, CLI(691) clears the
recorded interrupts for the specified interrupt inputs in Interrupt Input Unit 0.
Interrupt
input n
Internal
status
Recorded interrupt retained
Recorded interrupt cleared
Internal status
Interrupt input n
MSKS(690)
Execution of scheduled
interrupt task.
Time to first
scheduled interrupt
Name
Label
Operation
Error Flag
ER
ON if N is not within the specified range of 0 to 5 (0, 1, or
4 to 11 for CJ1M).
ON if C is not within the specified range of 0000 to 00FF
hex when N is 0 to 3 (for I/O interrupts and C200HS-INT
only).
ON if C is not 0000 or 0001 hex (for high-speed counter
interrupts and CJ1M built-in interrupt inputs only).
ON if C is not within the specified range of 0 to 9,999 dec-
imal (0000 to 270F hex) for scheduled interrupts.
OFF in all other cases.
Summary of Contents for SYSMAC CS1D-CPU**
Page 3: ...iv...
Page 29: ...xxx...
Page 185: ...146 List of Instructions by Function Code Section 2 4...
Page 1389: ...1350 CJ series Instruction Execution Times and Number of Steps Section 4 2...
Page 1390: ...1351 Appendix A ASCII Code Table ASCII SP Four leftmost bits Four rightmost bits...
Page 1391: ...1352 ASCII Code Table Appendix A...