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271
Timer and Counter Instructions
Section 3-6
Ladder Symbol
BCD
Binary
Variations
Applicable Program Areas
Operands
D1: Completion Flags
D1 contains the eight Completion Flags as well as the pause and reset bits.
D2: PV Word
D2 contains the 4-digit binary or BCD PV.
S: First SV Word
S through S+7 contain the eight independent SVs.
Each SV must be as follows:
MTIM(543)
D1
D2
S
D1
: Completion Flags
D2
: PV word
S
: First SV word
MTIMX(554)
D1
D2
S
D1
: Completion Flags
D2
: PV word
S
: First SV word
Variations
Executed Each Cycle for ON Condition
MTIM(543)/
MTIMX(554)
Executed Once for Upward Differentiation
Not supported.
Executed Once for Downward Differentiation
Not supported.
Immediate Refreshing Specification
Not supported.
Block program areas
Step program areas
Subroutines
Interrupt tasks
Not allowed
OK
OK
Not allowed
Data
Range
BCD
#0000 to #9999
Binary
&0 to &65535 (decimal)
#0000 to #FFFF (hex)
Data
Range
BCD
#0000 to #9999
Binary
&0 to &65535 (decimal)
#0000 to #FFFF (hex)
15
1
D1
9
8
6
4
2
7
5
3
0
Completion Flags
Reset bit
Do not use.
Pause bit
Summary of Contents for SYSMAC CS1D-CPU**
Page 3: ...iv...
Page 29: ...xxx...
Page 185: ...146 List of Instructions by Function Code Section 2 4...
Page 1389: ...1350 CJ series Instruction Execution Times and Number of Steps Section 4 2...
Page 1390: ...1351 Appendix A ASCII Code Table ASCII SP Four leftmost bits Four rightmost bits...
Page 1391: ...1352 ASCII Code Table Appendix A...