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696
Double-precision Floating-point Instructions (CS1-H, CJ1-H, CJ1M, or CS1D Only)
Section 3-16
Description
The input comparison instruction compares the data specified in S
1
and S
2
as
double-precision floating point values (64-bit IEEE754 data) and creates an
ON execution condition when the comparison condition is true. When the data
is stored in words, S
1
and S
2
specify the first of four words containing the 64-
bit data. The 64-bit floating-point data cannot be input as constants.
Inputting the Instructions
The input comparison instructions are treated just like the LD, AND, and OR
instructions to control the execution of subsequent instructions.
Indirect DM/EM
addresses in BCD
*D00000 to *D32767
*E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants
---
Data Registers
---
Index Registers
---
Indirect addressing
using Index Registers
,IR0 to ,IR15
–2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15
Area
S
1
S
2
Input type
Operation
LD
The instruction can be connected directly to the left bus bar.
AND
The instruction cannot be connected directly to the left bus bar.
OR
The instruction can be connected directly to the left bus bar.
<D
<D
<D
LD connection
AND connection
OR connection
ON execution condition when
comparison result is true.
ON execution condition when
comparison result is true.
ON execution condition when
comparison result is true.
Summary of Contents for SYSMAC CS1D-CPU**
Page 3: ...iv...
Page 29: ...xxx...
Page 185: ...146 List of Instructions by Function Code Section 2 4...
Page 1389: ...1350 CJ series Instruction Execution Times and Number of Steps Section 4 2...
Page 1390: ...1351 Appendix A ASCII Code Table ASCII SP Four leftmost bits Four rightmost bits...
Page 1391: ...1352 ASCII Code Table Appendix A...