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188
Sequence Output Instructions
Section 3-4
Description
If there is no immediate refreshing specification, the status of the execution
condition (power flow) is reversed and written to a specified bit in I/O memory.
If there is an immediate refreshing specification, the status of the execution
condition (power flow) is reversed and also written to the Basic Output Unit’s
output terminal in addition to the output bit in I/O memory.
Flags
There are no flags affected by this instruction.
Example
3-4-3
KEEP: KEEP(011)
Purpose
Operates as a latching relay.
Ladder Symbol
Holding Bit Area
H00000 to H51115
Auxiliary Bit Area
A44800 to A95915
Timer Area
---
Counter Area
---
TR Area
TR0 to TR15
DM Area
---
EM Area without bank
---
EM Area with bank
---
Indirect DM/EM
addresses in binary
---
Indirect DM/EM
addresses in BCD
---
Constants
---
Data Registers
---
Index Registers
---
Indirect addressing using
Index Registers
,IR0 to ,IR15
–2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to ,IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15
Area
OUT bit operand
Instruction
Operand
LD
000000
OUT
000001
OUT NOT
000002
KEEP(011)
B
S (Set)
R (Reset)
B
: Bit
Summary of Contents for SYSMAC CS1D-CPU**
Page 3: ...iv...
Page 29: ...xxx...
Page 185: ...146 List of Instructions by Function Code Section 2 4...
Page 1389: ...1350 CJ series Instruction Execution Times and Number of Steps Section 4 2...
Page 1390: ...1351 Appendix A ASCII Code Table ASCII SP Four leftmost bits Four rightmost bits...
Page 1391: ...1352 ASCII Code Table Appendix A...