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1131
Clock Instructions
Section 3-28
D and D+1: Result Data
D and D+1 contain the result data in seconds-only format. D and D+1 must be
in the same data area.
Operand Specifications
15
0
D
15
0
D+1
Rightmost 4 digits
Seconds: 0000 to 9999 (BCD)
Leftmost 4 digits
Seconds: 0000 to 3599 (BCD)
Area
S
D
CIO Area
CIO 0000 to CIO 6142
Work Area
W000 to W510
Holding Bit Area
H000 to H510
Auxiliary Bit Area
A000 to A958
A448 to A958
Timer Area
T0000 to T4094
Counter Area
C0000 to C4094
DM Area
D00000 to D32766
EM Area without bank
E00000 to E32766
EM Area with bank
En_00000 to En_32766
(n = 0 to C)
Indirect DM/EM
addresses in binary
@ D00000 to @ D32767
@ E00000 to @ E32767
@ En_00000 to @ En_32767
(n = 0 to C)
Indirect DM/EM
addresses in BCD
*D00000 to *D32767
*E00000 to *E32767
*En_00000 to *En_32767
(n = 0 to C)
Constants
Specified values only
---
Data Registers
---
Index Registers
---
Indirect addressing
using Index Registers
,IR0 to ,IR15
–2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15
Summary of Contents for SYSMAC CS1D-CPU**
Page 3: ...iv...
Page 29: ...xxx...
Page 185: ...146 List of Instructions by Function Code Section 2 4...
Page 1389: ...1350 CJ series Instruction Execution Times and Number of Steps Section 4 2...
Page 1390: ...1351 Appendix A ASCII Code Table ASCII SP Four leftmost bits Four rightmost bits...
Page 1391: ...1352 ASCII Code Table Appendix A...