164
Sequence Input Instructions
Section 3-3
Applicable Program Areas
Operand Specifications
Description
LD NOT is used for the first normally closed bit from the bus bar, or for the first
normally closed bit of a logic block. If there is no immediate refreshing specifi-
cation, the specified bit in I/O memory is read and reversed. If there is an
immediate refreshing specification, the status of the Basic Input Unit’s input
terminal is read, reversed, and used.
LD NOT is used in the following circumstances as an instruction for indicating
a logical start.
• When directly connecting to the bus bar.
• When logic blocks are connected by AND LD or OR LD. (Used at the
beginning of a logic block.)
The AND LOAD and OR LOAD instructions are used to connect in series or in
parallel logic blocks beginning with LD or LD NOT.
At least one LOAD or LOAD NOT instruction is required for the execution con-
dition when output-related instructions cannot be connected directly to the
bus bar. If there is no LOAD or LOAD NOT instruction, a program error will
occur with the program check by the Peripheral Device.
When logic blocks are connected by AND LOAD or OR LOAD instructions, the
total number of AND LOAD/OR LOAD instructions must match the total num-
ber of LOAD/LOAD NOT instructions minus1. If they do not match, a program-
ming error will occur.
Block program areas
Step program areas
Subroutines
Interrupt tasks
OK
OK
OK
OK
Area
LD NOT bit operand
CIO Area
CIO 000000 to CIO 614315
Work Area
W00000 to W51115
Holding Bit Area
H00000 to H51115
Auxiliary Bit Area
A00000 to A95915
Timer Area
T0000 to T4095
Counter Area
C0000 to C4095
Task Flag Area
TK0000 to TK0031
Condition Flags
ER, CY, N, OF, UF, >, =, <, >=, <>, <=, ON, OFF, AER
Clock Pulses
0.02 s, 0.1 s, 0.2 s, 1 s, 1 min
TR Area
---
DM Area
---
EM Area without bank
---
EM Area with bank
---
Indirect DM/EM
addresses in binary
---
Indirect DM/EM
addresses in BCD
---
Constants
---
Data Registers
---
Index Registers
---
Indirect addressing
using Index Registers
,IR0 to ,IR15
–2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15
Summary of Contents for SYSMAC CS1D-CPU**
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Page 185: ...146 List of Instructions by Function Code Section 2 4...
Page 1389: ...1350 CJ series Instruction Execution Times and Number of Steps Section 4 2...
Page 1390: ...1351 Appendix A ASCII Code Table ASCII SP Four leftmost bits Four rightmost bits...
Page 1391: ...1352 ASCII Code Table Appendix A...