908
High-speed Counter/Pulse Output Instructions
Section 3-21
F: Frequency
F specifies the frequency of the pulse output between 0.1 and 6,553.5 Hz
(0.1 Hz units, 0001 to FFFF hex). The accuracy of the PMW(891) waveform
that is actually output (ON duty +5%/
−
0%) applies only to 0.1 to 1,000.0 Hz
due to limitations in the output circuits.
D: Duty Factor
D specifies the duty factor of the pulse output, i.e., the percentage of time that
the output is ON. The value of D must be between the following range.
• Pre-Ver. 2.0 CJ1m CPU Units
0% and 100% (1% units, 0000 to 0064 hex)
• Ver. 2.0 CJ1m CPU Units
0.0% and 100.0% (0.1% units, 0000 to 03E8 hex)
Operand Specifications
Description
PWM(891) outputs the frequency specified in F at the duty factor specified in
D from the port specified in P. PWM(891) can be executed during duty-factor
pulse output to change the duty factor without stopping pulse output. Any
attempts to change the frequency will be ignored.
Pulse output is started each time PWM(891) is executed. It is thus normally
sufficient to use the differentiated version (@PWM(891)) of the instruction or
an execution condition that is turned ON only for one scan.
The pulse output will continue either until INI(880) is executed to stop it (C =
0003 hex: stop pulse output) or until the CPU Unit is switched to PROGRAM
mode.
Area
P
F
D
CIO Area
---
CIO 0000 to CIO 6143 CIO 0000 to CIO 6143
Work Area
---
W000 to W511
W000 to W511
Holding Bit Area
---
H000 to H511
H000 to H511
Auxiliary Bit Area
---
A448 to A959
A448 to A959
Timer Area
---
T0000 to T4095
T0000 to T4095
Counter Area
---
C0000 to C4095
C0000 to C4095
DM Area
---
D00000 to D32767
D00000 to D32767
EM Area without bank ---
---
---
EM Area with bank
---
---
---
Indirect DM/EM
addresses in binary
---
@ D00000 to @
D32767
@ D00000 to @
D32767
Indirect DM/EM
addresses in BCD
---
*D00000 to *D32767
*D00000 to *D32767
Constants
See
descrip-
tion of
operand.
0000 to FFFF hex
0000 to 0064 hex
Data Registers
---
DR0 to DR15
DR0 to DR15
Index Registers
---
---
---
Indirect addressing
using Index Registers
---
,IR0 to ,IR15
–2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15
Summary of Contents for SYSMAC CS1D-CPU**
Page 3: ...iv...
Page 29: ...xxx...
Page 185: ...146 List of Instructions by Function Code Section 2 4...
Page 1389: ...1350 CJ series Instruction Execution Times and Number of Steps Section 4 2...
Page 1390: ...1351 Appendix A ASCII Code Table ASCII SP Four leftmost bits Four rightmost bits...
Page 1391: ...1352 ASCII Code Table Appendix A...