![background image](http://html1.mh-extra.com/html/omron/sysmac-cs1d-cpu/sysmac-cs1d-cpu_reference-manual_742268397.webp)
358
Data Movement Instructions
Section 3-8
Applicable Program Areas
Operands
D: Destination
The destination must be an Index Register (IR0 to IR15).
Operand Specifications
Description
MOVR(560) finds the PLC memory address (absolute address) of S and
writes that address in D (an Index Register).
If a timer or counter is specified in S, MOVR(560) will write the PLC memory
address of the timer/counter Completion Flag in D. Use MOVRW(561) to write
the PLC memory address of the timer/counter PV in D.
Block program areas
Step program areas
Subroutines
Interrupt tasks
OK
OK
OK
OK
Area
S
D
CIO Area
CIO 0000 to CIO 6143
CIO 000000 to CIO 614315
---
Work Area
W000 to W511
W00000 to W51115
---
Holding Bit Area
H000 to H511
H00000 to H51115
---
Auxiliary Bit Area
A000 to A447
A448 to A959
A00000 to A44715
A44800 to A95915
---
Timer Area
T0000 to T4095
(Completion Flag)
---
Counter Area
C0000 to C4095
(Completion Flag)
---
Task Flag
TK0000 to TK0031
---
DM Area
D00000 to D32767
---
EM Area without bank
E00000 to E32767
---
EM Area with bank
En_00000 to En_32767
(n = 0 to C)
---
Indirect DM/EM
addresses in binary
---
Indirect DM/EM
addresses in BCD
---
Constants
---
Data Registers
---
Index Registers
---
IR0 to IR15
Indirect addressing
using Index Registers
---
Internal I/O memory address of S
Index Register
Summary of Contents for SYSMAC CS1D-CPU**
Page 3: ...iv...
Page 29: ...xxx...
Page 185: ...146 List of Instructions by Function Code Section 2 4...
Page 1389: ...1350 CJ series Instruction Execution Times and Number of Steps Section 4 2...
Page 1390: ...1351 Appendix A ASCII Code Table ASCII SP Four leftmost bits Four rightmost bits...
Page 1391: ...1352 ASCII Code Table Appendix A...