![background image](http://html1.mh-extra.com/html/omron/sysmac-cs1d-cpu/sysmac-cs1d-cpu_reference-manual_7422681167.webp)
1128
Clock Instructions
Section 3-28
T and T+1: Time Data
Set the time data in T and T+1 as shown in the following diagram. T and T+1
must be in the same data area.
R through R+2: Result Data
R through R+2 contain the result of the addition. R through R+2 must be in the
same data area.
Operand Specifications
15
8
0
7
T
15
0
T+1
Seconds: 00 to 59 (BCD)
Minutes: 00 to 59 (BCD)
Hours: 0000 to 9999 (BCD)
15
8
0
7
R
15
8
0
7
R+1
15
8
0
7
R+2
Seconds: 00 to 59 (BCD)
Minutes: 00 to 59 (BCD)
Hour: 00 to 23 (BCD)
Day: 01 to 31 (BCD)
Month: 01 to 12 (BCD)
Year: 00 to 99 (BCD)
Area
C
T
R
CIO Area
CIO 0000 to
CIO 6141
CIO 0000 to
CIO 6142
CIO 0000 to
CIO 6141
Work Area
W000 to W509
W000 to W510
W000 to W509
Holding Bit Area
H000 to H509
H000 to H510
H000 to H509
Auxiliary Bit Area
A000 to A957
A000 to A958
A448 to A957
Timer Area
T0000 to T4093
T0000 to T4094
T0000 to T4093
Counter Area
C0000 to C4093
C0000 to C4094
C0000 to C4093
DM Area
D00000 to
D32765
D00000 to
D32766
D00000 to
D32765
Summary of Contents for SYSMAC CS1D-CPU**
Page 3: ...iv...
Page 29: ...xxx...
Page 185: ...146 List of Instructions by Function Code Section 2 4...
Page 1389: ...1350 CJ series Instruction Execution Times and Number of Steps Section 4 2...
Page 1390: ...1351 Appendix A ASCII Code Table ASCII SP Four leftmost bits Four rightmost bits...
Page 1391: ...1352 ASCII Code Table Appendix A...