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Double-precision Floating-point Instructions (CS1-H, CJ1-H, CJ1M, or CS1D Only)
Section 3-16
Flags
Precautions
The augend (Au to Au+3) and Addend (Ad to Ad+3) data must be in IEEE754
floating-point data format.
3-16-6 DOUBLE FLOATING-POINT SUBTRACT: –D(846)
Purpose
Subtracts one double-precision (64-bit) floating-point number from another
and places the result in the specified destination words.
This instruction is supported by CS1-H, CJ1-H, CJ1M, and CS1D CPU Units
only.
Ladder Symbol
Variations
Applicable Program Areas
Operand Specifications
Name
Label
Operation
Error Flag
ER
ON if the augend or addend data is not recognized as
floating-point data.
ON if the augend or addend data is not a number (NaN).
ON if +
∞
is to –
∞
.
OFF in all other cases.
Equals Flag
=
ON if both the exponent and mantissa of the result are 0.
OFF in all other cases.
Overflow Flag
OF
ON if the absolute value of the result is too large to be
expressed as a double-precision floating-point value.
Underflow Flag
UF
ON if the absolute value of the result is too small to be
expressed as a double-precision floating-point value.
Negative Flag
N
ON if the result is negative.
OFF in all other cases.
–D(846)
D
Mi
Su
Mi
: First Minuend word
Su
: First Subtrahend word
D
: First destination word
Variations
Executed Each Cycle for ON Condition
–D(846)
Executed Once for Upward Differentiation
@–D(846)
Executed Once for Downward Differentiation
Not supported.
Immediate Refreshing Specification
Not supported.
Block program areas
Step program areas
Subroutines
Interrupt tasks
OK
OK
OK
OK
Area
Mi
Su
D
CIO Area
CIO 0000 to CIO 6140
Work Area
W000 to W508
Holding Bit Area
H000 to H508
Auxiliary Bit Area
A000 to A956
A448 to A956
Timer Area
T0000 to T4092
Counter Area
C0000 to C4092
DM Area
D00000 to D32764
EM Area without bank
E00000 to E32764
Summary of Contents for SYSMAC CS1D-CPU**
Page 3: ...iv...
Page 29: ...xxx...
Page 185: ...146 List of Instructions by Function Code Section 2 4...
Page 1389: ...1350 CJ series Instruction Execution Times and Number of Steps Section 4 2...
Page 1390: ...1351 Appendix A ASCII Code Table ASCII SP Four leftmost bits Four rightmost bits...
Page 1391: ...1352 ASCII Code Table Appendix A...