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881
High-speed Counter/Pulse Output Instructions
Section 3-21
Operand Specifications
Description
CTBL(882) registers a comparison table or registers and comparison table
and starts comparison for the port specified in P and the method specified in
C. Once a comparison table is registered, it is valid until a different table is
registered or until the CPU Unit is switched to PROGRAM mode.
Each time CTBL(882) is executed, comparison is started under the specified
conditions. When using CTBL(882) to start comparison, it is normally suffi-
cient to use the differentiated version (@CTBL(882)) of the instruction or an
execution condition that is turned ON only for one scan.
Note
If an interrupt task that has not been registered is specified, a fatal program
error will occur the first time an interrupt is generated.
■
Registering a Comparison Table (C = 0002 or 0003 hex)
If C is set to 0002 or 0003 hex, a comparison table will be registered, but com-
parison will not be started. Comparison is started with INI(880).
■
Registering a Comparison Table and Starting Comparison (C = 0000 or
0001 hex)
If C is set to 0000 or 0001 hex, a comparison table will be registered, and
comparison will be started.
■
Stopping Comparison
Comparison is stopped with INI(880). It makes no difference what instruction
was used to start comparison.
Area
P
C
TB
CIO Area
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---
CIO 0000 to CIO 6143
Work Area
---
---
W000 to W511
Holding Bit Area
---
---
H000 to H511
Auxiliary Bit Area
---
---
A448 to A959
Timer Area
---
---
T0000 to T4095
Counter Area
---
---
C0000 to C4095
DM Area
---
---
D00000 to D32767
EM Area without bank
---
---
---
EM Area with bank
---
---
---
Indirect DM/EM
addresses in binary
---
---
@ D00000 to @ D32767
Indirect DM/EM
addresses in BCD
---
---
*D00000 to *D32767
Constants
See descrip-
tion of oper-
and.
See descrip-
tion of oper-
and.
---
Data Registers
---
---
---
Index Registers
---
---
---
Indirect addressing
using Index Registers
---
---
,IR0 to ,IR15
–2048 to +2047 ,IR0 to
–2048 to +2047 ,IR15
DR0 to DR15, IR0 to
IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15
Summary of Contents for SYSMAC CS1D-CPU**
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Page 185: ...146 List of Instructions by Function Code Section 2 4...
Page 1389: ...1350 CJ series Instruction Execution Times and Number of Steps Section 4 2...
Page 1390: ...1351 Appendix A ASCII Code Table ASCII SP Four leftmost bits Four rightmost bits...
Page 1391: ...1352 ASCII Code Table Appendix A...