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Interrupt Control Instructions
Section 3-20
When a CS1D CPU Unit for Single-CPU System or a CS1-H, CJ1-H, or CJ1M
CPU Unit is being used, the power OFF interrupt task is disabled, and A530 is
set to A5A5 hex, the CPU Unit will be reset after execution of EI(694) in the
event that a power interruption is detected during execution of the instructions
between DI(693) and EI(694).
Examples
When CIO 000000 is ON in the following example, DI(693) disables all inter-
rupt tasks other than the power OFF interrupt task.
DI
END
DI
END
DI instruction is valid.
Interrupt tasks are executed under
registered conditions.
DI instruction is valid.
Task No. 0
Task No. 1
DI
END
EI
END
The mask on power
OFF interrupt
processing is enabled.
Task No. 0
Task No. 1
000000
Disables execution of all interrupt tasks
(except the power OFF interrupt).
With CS1D CPU Units for Single-CPU
Systems or CS1-H, CJ1-H, or CJ1M
CPU Units:
Power OFF interrupt processing can be
disabled at the same time if the power
OFF interrupt task is disabled.
Summary of Contents for SYSMAC CS1D-CPU**
Page 3: ...iv...
Page 29: ...xxx...
Page 185: ...146 List of Instructions by Function Code Section 2 4...
Page 1389: ...1350 CJ series Instruction Execution Times and Number of Steps Section 4 2...
Page 1390: ...1351 Appendix A ASCII Code Table ASCII SP Four leftmost bits Four rightmost bits...
Page 1391: ...1352 ASCII Code Table Appendix A...