275
Timer and Counter Instructions
Section 3-6
D1: 0100CH
D2: D00100
S: D00200
S+1: D00201
S+2: D00202
S+3: D00203
S+4: D00204
S+5: D00205
S+6: D00206
S+7: D00207
Reset bit
Completion Flags
Timer PV
Timer SVs
(Incrementing)
Pause bit
Corresponding completion
flag ON when SV
≤
PV.
CIO 000000
CIO 010008
CIO 010009
SV 7
SV 1
SV 0
Timer input
Timer SVs
Reset bit
PV maintained.
Timing resumes.
Completion Flags
Pause bit
Max. PV = 9999
Timer input must remain ON
while the timer is timing.
Summary of Contents for SYSMAC CS1D-CPU**
Page 3: ...iv...
Page 29: ...xxx...
Page 185: ...146 List of Instructions by Function Code Section 2 4...
Page 1389: ...1350 CJ series Instruction Execution Times and Number of Steps Section 4 2...
Page 1390: ...1351 Appendix A ASCII Code Table ASCII SP Four leftmost bits Four rightmost bits...
Page 1391: ...1352 ASCII Code Table Appendix A...