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659
Double-precision Floating-point Instructions (CS1-H, CJ1-H, CJ1M, or CS1D Only)
Section 3-16
Description
FIXD(841) converts the integer portion of the double-precision (64-bit) float-
ing-point number in words S to S+3 (IEEE754-format) to 16-bit signed binary
data and places the result in D.
Only the integer portion of the floating-point data is converted, and the fraction
portion is truncated. The integer portion of the floating-point data must be
within the range of –32,768 to 32,767.
Example conversions:
A floating-point value of 3.5 is converted to 3.
A floating-point value of –3.5 is converted to –3.
Flags
3-16-2 DOUBLE FLOATING TO 32-BIT: FIXLD(842)
Purpose
Converts a double-precision (64-bit) floating-point value to 32-bit signed
binary data and places the result in the specified result words.
This instruction is supported by CS1-H, CJ1-H, CJ1M, and CS1D CPU Units
only.
Ladder Symbol
Variations
Applicable Program Areas
Operand Specifications
S+3CH
SCH
DCH
S+1CH
S+2CH
Floating-point data (64 bits)
Signed binary data (16 bits)
Name
Label
Operation
Error Flag
ER
ON if the source data (S to S+3) is not a number (NaN).
ON if the integer portion of the source data (S to S+3) is
not within the range of –32,768 to 32,767.
OFF in all other cases.
Equals Flag
=
ON if the result is 0000.
OFF in all other cases.
Negative Flag
N
ON if bit 15 of the result is ON.
OFF in all other cases.
FIXDL(842)
S
D
S
: First source word
D
: First destination word
Variations
Executed Each Cycle for ON Condition
FIXLD(842)
Executed Once for Upward Differentiation
@FIXLD(842)
Executed Once for Downward Differentiation
Not supported.
Immediate Refreshing Specification
Not supported.
Block program areas
Step program areas
Subroutines
Interrupt tasks
OK
OK
OK
OK
Area
S
D
CIO Area
CIO 0000 to CIO 6140
CIO 0000 to CIO 6142
Work Area
W000 to W508
W000 to W510
Summary of Contents for SYSMAC CS1D-CPU**
Page 3: ...iv...
Page 29: ...xxx...
Page 185: ...146 List of Instructions by Function Code Section 2 4...
Page 1389: ...1350 CJ series Instruction Execution Times and Number of Steps Section 4 2...
Page 1390: ...1351 Appendix A ASCII Code Table ASCII SP Four leftmost bits Four rightmost bits...
Page 1391: ...1352 ASCII Code Table Appendix A...